From 3f0c967c3d51ba37c7496c948321a502e9b3259e Mon Sep 17 00:00:00 2001 From: megacz Date: Thu, 26 Feb 2009 14:29:07 -0800 Subject: [PATCH] added code to implement FORWARD_LATENCY using srl16 --- src/edu/berkeley/fleet/fpga/verilog/Verilog.java | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java index 1393c55..f0a25d4 100644 --- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java +++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java @@ -42,6 +42,10 @@ import static edu.berkeley.fleet.two.FleetTwoFleet.*; */ public class Verilog { + //public static final int FORWARD_LATENCY = 1; + public static final int FORWARD_LATENCY = 6; + public static final int REVERSE_LATENCY = 3; + public static interface Value { public String getVerilog(); public Value getBits(int high, int low); @@ -566,7 +570,23 @@ public class Verilog { public String getAssignments() { StringBuffer sb = new StringBuffer(); if (external) { - sb.append("assign " + name +"_r_ = " + name + "_r;\n"); + int a = FORWARD_LATENCY - 1; + if (a<0 || a>16) { + throw new RuntimeException("cannot offer latency of " + FORWARD_LATENCY +"-1"); + } else if (a==0) { + sb.append("assign " + name +"_r_ = " + name + "_r;\n"); + } else { + a = a-1; // CLK-to-Q gives us one cycle of latency anyways + sb.append("SRL16E srl16_"+name+"_r\n"); + sb.append(" (.Q ("+name+"_r_),\n"); + sb.append(" .A0 ("+((a & (1<<0)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .A1 ("+((a & (1<<1)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .A2 ("+((a & (1<<2)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .A3 ("+((a & (1<<3)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .CE (1),\n"); + sb.append(" .CLK (clk),\n"); + sb.append(" .D ("+name+"_r));\n"); + } sb.append("assign " + name +"_ = " + name + ";\n"); } if (controlDriver != null) { -- 1.7.10.4