From 4756e75ee30de9fe4a5c3cd762a3cd4f04d97845 Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Fri, 1 May 2009 00:08:45 +0000 Subject: [PATCH] new files from Ivan, 30-Apr --- electric/loopCountM.jelib | 153 +- electric/moveM.jelib | 30 +- electric/predicateM.jelib | 40 +- electric/stagesM.jelib | 8 +- .../com/sun/vlsi/chips/marina/test/MarinaTest.java | 2 - testCode/marina.spi | 2004 +++++++++++--------- testCode/marina.v | 108 +- 7 files changed, 1284 insertions(+), 1061 deletions(-) diff --git a/electric/loopCountM.jelib b/electric/loopCountM.jelib index f4577b3..a0ee2f9 100755 --- a/electric/loopCountM.jelib +++ b/electric/loopCountM.jelib @@ -1949,7 +1949,7 @@ Echeck[T_1]|zero|D4G2;|conn@24|a|I X # Cell loadORcount;1{ic} -CloadORcount;1{ic}||artwork|1240670646209|1240677254555|E +CloadORcount;1{ic}||artwork|1240670646209|1241048450487|E Ngeneric:Facet-Center|art@0||0|0||||AV Nschematic:Bus_Pin|pin@1||-6|3|-1|-1|| Nschematic:Bus_Pin|pin@2||6|0|-1|-1|| @@ -1996,7 +1996,7 @@ AThicker|net@22|||FS1800|pin@29||5|0|pin@30||6|0 Aschematic:bus|net@24||-0.5|IJ1800|pin@32||5|-3|pin@6||6|-3 AThicker|net@30|||FS0|pin@13||5|-4|pin@10||-5|-4 Edo[ins]||D5G2;|pin@1||I -Edo[reD]||D5G2;|pin@2||I +Edo[reD]|doneLO[M]|D5G2;|pin@2||I Eflag[D][set,clr]||D5G2;|pin@3||O Eilc[load]||D5G2;|pin@4||O Emc||D5G2;|pin@5||I @@ -2133,7 +2133,7 @@ Evdd_24||D5G5;|pinsVddG@5|vdd_1|P X # Cell loadORcount;4{sch} -CloadORcount;4{sch}||schematic|1230935566337|1240688051832| +CloadORcount;4{sch}||schematic|1230935566337|1241048454810| Ngeneric:Facet-Center|art@0||0|0||||AV NOff-Page|conn@3||6|-13|||YRRR| NOff-Page|conn@5||9|15|||XR| @@ -2143,7 +2143,7 @@ NOff-Page|conn@8||3|13|||R| NOff-Page|conn@9||-15|7|||XR| NOff-Page|conn@11||-33|0|||XR| NOff-Page|conn@13||-50|-6|||XYRR| -NOff-Page|conn@14||-6.5|-10|||XY| +NOff-Page|conn@14||-7.5|-10|||XY| IilcLoad;1{ic}|ilcLoad@0||-36|-12|||D5G4; IloadORcount;1{ic}|loadORco@0||24|18|||D5G4; IolcControlD;1{ic}|olcContr@1||6|6|||D5G4; @@ -2200,7 +2200,7 @@ Awire|net@909|||0|olcCount@0|sel[Co]|25|-14|pin@388||21|-14 Abus|net@912||-0.5|IJ900|conn@8|a|3|11|olcContr@1|flag[D][set,clr]|3|9 Abus|net@913||-0.5|IJ2700|olcContr@1|s[2,3]|9|10|conn@5|a|9|13 Awire|net@916|||1800|conn@13|y|-48|-6|pin@383||-45|-6 -Awire|net@917|||0|conn@14|y|-8.5|-10|olcLoad@0|do[reD]|-12|-10 +Awire|net@917|||0|conn@14|y|-9.5|-10|olcLoad@0|do[reD]|-12|-10 Awire|net@918|||0|wire90@1|a|13|0|pin@371||9|0 Awire|net@919|||0|pin@370||27|0|wire90@1|b|18|0 Awire|net@920|||0|pin@368||3|0|wire90@0|b|-4|0 @@ -2213,7 +2213,7 @@ Awire|sel[Ld]|D5G2;||900|pin@384||-45|-14|pin@385||-45|-17 Awire|sel[Ld]|D5G2;||900|pin@386||-27|-14|pin@387||-27|-17 Awire|sel[rD]|D5G2;||900|pin@373||-39|-20.5|pin@392||-39|-24 Emc_1|do[ins]|D4G2;|conn@13|a|I -Edo[reD]||D4G2;|conn@14|a|I +Edo[reD]|doneLO[M]|D4G2;|conn@14|a|I Eflag[D][set,clr]||D6G2;|conn@8|y|O Eilc[load]||D6G2;|conn@11|y|O Emc||D4G2;|conn@6|a|I @@ -4208,7 +4208,7 @@ Eload[2]|load[T]|D4G2;|conn@7|a|I X # Cell olcLoad;1{ic} -ColcLoad;1{ic}||artwork|1240668640419|1240688007944|E +ColcLoad;1{ic}||artwork|1240668640419|1241048222386|E Ngeneric:Facet-Center|art@0||0|0||||AV Nschematic:Bus_Pin|pin@0||-3|-4|-1|-1|| Nschematic:Bus_Pin|pin@1||-6|2|-1|-1|| @@ -4255,7 +4255,7 @@ AThicker|net@18|||FS1800|pin@15||-3|-3|pin@10||5|-3 AThicker|net@19|||FS1800|pin@11||-4|3|pin@26||0|3 AThicker|net@20|||FS2700|pin@26||0|3|pin@27||0|5 Edo[ins]||D5G2;|pin@1||I -Edo[reD]||D5G2;|pin@2||I +Edo[reD]|doneLO[M]|D5G2;|pin@2||I Efire[zz]||D5G2;|pin@3||O Emc||D5G2;|pin@4||I Eolc[load]||D5G2;|pin@5||O @@ -4448,49 +4448,38 @@ Evdd_9|vdd_7|D5G2;|sucDri10@0|vdd_3|P X # Cell olcLoad;4{sch} -ColcLoad;4{sch}||schematic|1230935566337|1241023276524| +ColcLoad;4{sch}||schematic|1230935566337|1241048862524| Ngeneric:Facet-Center|art@0||0|0||||AV NOff-Page|conn@6||-60|33|||XYR| NOff-Page|conn@7||-109.5|26|||Y| NOff-Page|conn@9||-84|12|||XR| NOff-Page|conn@12||-108|-24|||XYRR| -NOff-Page|conn@14||-18|31.5|||XR| +NOff-Page|conn@14||-6|31.5|||XR| NOff-Page|conn@15||-107.5|-19|||XYRR| -NOff-Page|conn@16||22|26|||XY| +NOff-Page|conn@16||2.5|12|||XY| IcentersJ:ctrAND3in100A;1{ic}|ctrAND3i@2||-84|-3|R||D5G4; -IredFive:inv;1{ic}|inv@26||-12|6|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:inv;1{ic}|inv@27||14.5|-12|RR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:inv;1{ic}|inv@28||-24|6|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 +IredFive:inv;1{ic}|inv@28||-18|6|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:inv;1{ic}|inv@30||-100|-24|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:inv;1{ic}|inv@32||-49.5|12|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:inv;1{ic}|inv@33||0|5.5|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:inv;1{ic}|inv@34||-36|4.5|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:invI;2{ic}|invI@6||0|-6|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:invI;2{ic}|invI@7||-36|-6|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:invI;2{ic}|invI@8||-36|18|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:invI;2{ic}|invI@9||0|18|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:invI;2{ic}|invI@10||6.5|12|XRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:invI;2{ic}|invI@11||-39.5|12|RR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 +IredFive:inv;1{ic}|inv@34||-30|4.5|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 +IredFive:invI;2{ic}|invI@7||-30|-6|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 +IredFive:invI;2{ic}|invI@8||-30|18|XR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 +IredFive:invI;2{ic}|invI@11||-18|18|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:nand2;1{ic}|nand2@5||-100|-18|||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:nand2;1{ic}|nand2@7||-48|-11|Y||D0G4;|ATTR_Delay(D5G1;NPX2.5;Y-3;)I100|ATTR_X(D5G1.5;NPX2.5;Y2.5;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 -IredFive:nand2n_sy;1{ic}|nand2n_s@1||-18|18|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2.5;)I100|ATTR_X(D5G1.5;NPX2;Y2.5;)S6|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 +IredFive:nand2n_sy;1{ic}|nand2n_s@1||-6|18|R||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2.5;)I100|ATTR_X(D5G1.5;NPX2;Y2.5;)S6|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IolcLoad;1{ic}|olcLoad@0||-38|45|||D5G4; Ngeneric:Invisible-Pin|pin@0||-63|48.5|||||ART_message(D5G5;)SolcLoad -Ngeneric:Invisible-Pin|pin@1||-63|42.5|||||ART_message(D5G3;)Sies 25 April 2009 -Ngeneric:Invisible-Pin|pin@124||-26|46|||||ART_message(D3G2;)S["fire[zz] stage sets flag[D]","from the olc[zero] value.","Use after olc[load] or to",restore D after move.] -NWire_Pin|pin@244||18|26|||| +Ngeneric:Invisible-Pin|pin@1||-63|42.5|||||ART_message(D5G3;)Sies 29 April 2009 +Ngeneric:Invisible-Pin|pin@124||-26|46|||||ART_message(D3G2;)S["fire[zz] stage sets flag[D]","from the olc[zero] value.","Use after olc[load] or to",restore D as last act of move.] NWire_Pin|pin@257||-105|-17|||| -NWire_Pin|pin@310||18|-12|||X| NWire_Pin|pin@364||-60|8|||X| -NWire_Pin|pin@372||0|0|||| -NWire_Pin|pin@374||-17|12|||| -NWire_Pin|pin@379||-24|0|||X| -NWire_Pin|pin@380||-24|12|||X| -NWire_Pin|pin@381||-19|12|||| -NWire_Pin|pin@383||-36|0|||| -NWire_Pin|pin@390||-36|24|||| -NWire_Pin|pin@392||0|24|||| -NWire_Pin|pin@393||0|-12|||| +NWire_Pin|pin@374||-5|12|||| +NWire_Pin|pin@379||-18|0|||X| +NWire_Pin|pin@380||-18|12|||X| +NWire_Pin|pin@381||-7|12|||| +NWire_Pin|pin@383||-30|0|||| +NWire_Pin|pin@390||-30|24|||| Ngeneric:Invisible-Pin|pin@399||-110.5|-26.5|||||ART_message(D3G2;)S["sel[rD] selects what to load","1 = olc, 0 = ilc"] NWire_Pin|pin@405||-72|6|||| NWire_Pin|pin@406||-86.5|-18|||| @@ -4499,60 +4488,41 @@ NWire_Pin|pin@408||-81.5|-12|||| NWire_Pin|pin@409||-72|-12|||| NWire_Pin|pin@411||-84|6|||| NWire_Pin|pin@415||-105|26|||| -NWire_Pin|pin@416||-36|-11|||| +NWire_Pin|pin@416||-30|-11|||| NWire_Pin|pin@420||-60|4|||| NWire_Pin|pin@421||-60|-18|||| NWire_Pin|pin@426||-54|0|||| NWire_Pin|pin@427||-54|-10|||| -NWire_Pin|pin@431||-36|12|||| -NWire_Pin|pin@432||-12|12|||| -NWire_Pin|pin@433||-12|0|||| +NWire_Pin|pin@431||-30|12|||| NWire_Pin|pin@434||-45|12|||| NWire_Pin|pin@435||-45|0|||| NWire_Pin|pin@436||-54|12|||| NWire_Pin|pin@437||-54|24|||| -NWire_Pin|pin@439||-60|28|||| -NWire_Pin|pin@441||0|12|||| -Ngeneric:Invisible-Pin|pin@442||-18|-7.5|||||ART_message(D5G2;)Sextra load to limit speed +Ngeneric:Invisible-Pin|pin@442||-31.5|-16.5|||||ART_message(D5G2;)Sextra load to limit speed +Ngeneric:Invisible-Pin|pin@443||-4|8.5|||||ART_message(D3G2;)S["doneLO[M] is",the last move event] IdriversM:predDri10wMC;1{ic}|predDri1@0||-67|6|XY||D5G4; -IdriversM:predDri20wMC;1{ic}|predDri2@3||12|26|Y||D5G4; IdriversM:predDri40;1{ic}|predDri4@0||-98|24|X||D5G4; IdriversM:sucDri10;1{ic}|sucDri10@1||-77.5|6|||D5G4; IorangeTSMC090nm:wire90;1{ic}|wire90@17||-41.5|-11|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@22||7|-12|X||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@25||-93|-18|||D0G4;|ATTR_L(D5G1;PUD)D140.59999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@39||-46.5|24|||D0G4;|ATTR_L(D5G1;PUD)D144.29999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@40||-6|0|||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@41||-6|12|||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@42||-30|0|||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@47||4.5|24|||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 +IorangeTSMC090nm:wire90;1{ic}|wire90@42||-24|0|||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@48||-93|-24|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@50||-77|-12|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@51||-49|0|||D0G4;|ATTR_L(D5G1;PUD)D431.29999999999995|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@52||-30|12|X||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 +IorangeTSMC090nm:wire90;1{ic}|wire90@52||-24|12|X||D0G4;|ATTR_L(D5G1;PUD)D215.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 Awire|do[2]|D5G2;||900|pin@405||-72|6|pin@409||-72|-12 -Awire|net@563|||1800|predDri2@3|pred|15|26|pin@244||18|26 Awire|net@845|||1800|predDri1@0|mc|-64|8|pin@364||-60|8 -Awire|net@880|||1800|inv@27|in|17|-12|pin@310||18|-12 -Awire|net@885|||1800|wire90@22|a|9.5|-12|inv@27|out|12|-12 -Awire|net@887|||1800|wire90@40|b|-3.5|0|pin@372||0|0 -Awire|net@889|||0|wire90@40|a|-8.5|0|pin@433||-12|0 -Awire|net@891|||0|pin@432||-12|12|pin@374||-17|12 -Awire|net@898|||2700|pin@374||-17|12|nand2n_s@1|ina|-17|15.5 -Awire|net@905|||1800|wire90@42|b|-27.5|0|pin@379||-24|0 -Awire|net@906|||2700|pin@379||-24|0|inv@28|in|-24|3.5 -Awire|net@908|||900|pin@380||-24|12|inv@28|out|-24|8.5 -Awire|net@910|||2700|pin@381||-19|12|nand2n_s@1|inb|-19|15.5 -Awire|net@913|||2700|invI@7|out|-36|-3.5|pin@383||-36|0 -Awire|net@914|||1800|pin@383||-36|0|wire90@42|a|-32.5|0 -Awire|net@929|||900|invI@7|in|-36|-8.5|pin@416||-36|-11 -Awire|net@937|||0|pin@390||-36|24|wire90@39|b|-44|24 -Awire|net@938|||2700|invI@9|out|0|20.5|pin@392||0|24 -Awire|net@940|||900|invI@6|in|0|-8.5|pin@393||0|-12 -Awire|net@942|||0|wire90@22|b|4.5|-12|pin@393||0|-12 -Awire|net@945|||0|wire90@47|a|2|24|pin@392||0|24 -Awire|net@946|||1800|wire90@47|b|7|24|predDri2@3|in|9|24 -Awire|net@955|||900|conn@14|a|-18|29.5|nand2n_s@1|out|-18|20.5 +Awire|net@898|||2700|pin@374||-5|12|nand2n_s@1|ina|-5|15.5 +Awire|net@905|||1800|wire90@42|b|-21.5|0|pin@379||-18|0 +Awire|net@906|||2700|pin@379||-18|0|inv@28|in|-18|3.5 +Awire|net@908|||900|pin@380||-18|12|inv@28|out|-18|8.5 +Awire|net@910|||2700|pin@381||-7|12|nand2n_s@1|inb|-7|15.5 +Awire|net@913|||2700|invI@7|out|-30|-3.5|pin@383||-30|0 +Awire|net@914|||1800|pin@383||-30|0|wire90@42|a|-26.5|0 +Awire|net@929|||900|invI@7|in|-30|-8.5|pin@416||-30|-11 +Awire|net@937|||0|pin@390||-30|24|wire90@39|b|-44|24 +Awire|net@955|||900|conn@14|a|-6|29.5|nand2n_s@1|out|-6|20.5 Awire|net@956|||1800|nand2@5|out|-97.5|-18|wire90@25|a|-95.5|-18 Awire|net@957|||1800|pin@257||-105|-17|nand2@5|inb|-102.5|-17 Awire|net@964|||0|nand2@5|ina|-102.5|-19|conn@15|y|-105.5|-19 @@ -4570,7 +4540,7 @@ Awire|net@992|||0|sucDri10@1|in|-81.5|6|pin@411||-84|6 Awire|net@998|||0|predDri4@0|pred|-100|26|pin@415||-105|26 Awire|net@999|||0|pin@415||-105|26|conn@7|y|-107.5|26 Awire|net@1001|||2700|pin@257||-105|-17|pin@415||-105|26 -Awire|net@1005|||1800|wire90@17|b|-39|-11|pin@416||-36|-11 +Awire|net@1005|||1800|wire90@17|b|-39|-11|pin@416||-30|-11 Awire|net@1015|||0|predDri1@0|pred|-70|6|pin@405||-72|6 Awire|net@1016|||1800|predDri1@0|in|-64|4|pin@420||-60|4 Awire|net@1017|||900|pin@420||-60|4|pin@421||-60|-18 @@ -4583,34 +4553,23 @@ Awire|net@1035|||0|wire90@51|a|-51.5|0|pin@426||-54|0 Awire|net@1036|||900|pin@426||-54|0|pin@427||-54|-10 Awire|net@1037|||1800|pin@427||-54|-10|nand2@7|ina|-50.5|-10 Awire|net@1040|||0|nand2@7|inb|-50.5|-12|pin@409||-72|-12 -Awire|net@1045|||1800|wire90@52|a|-27.5|12|pin@380||-24|12 -Awire|net@1046|||0|wire90@52|b|-32.5|12|pin@431||-36|12 -Awire|net@1047|||2700|pin@431||-36|12|invI@8|in|-36|15.5 -Awire|net@1048|||1800|pin@380||-24|12|pin@381||-19|12 -Awire|net@1049|||0|wire90@41|a|-8.5|12|pin@432||-12|12 -Awire|net@1050|||2700|inv@26|out|-12|8.5|pin@432||-12|12 -Awire|net@1052|||900|inv@26|in|-12|3.5|pin@433||-12|0 -Awire|net@1053|||2700|invI@6|out|0|-3.5|pin@372||0|0 -Awire|net@1054|||0|conn@16|y|20|26|pin@244||18|26 -Awire|net@1055|||900|pin@244||18|26|pin@310||18|-12 -Awire|net@1056|||900|pin@390||-36|24|invI@8|out|-36|20.5 +Awire|net@1045|||1800|wire90@52|a|-21.5|12|pin@380||-18|12 +Awire|net@1046|||0|wire90@52|b|-26.5|12|pin@431||-30|12 +Awire|net@1047|||2700|pin@431||-30|12|invI@8|in|-30|15.5 +Awire|net@1048|||1800|pin@380||-18|12|pin@381||-7|12 +Awire|net@1056|||900|pin@390||-30|24|invI@8|out|-30|20.5 Awire|net@1057|||1800|inv@32|out|-47|12|pin@434||-45|12 Awire|net@1058|||900|pin@434||-45|12|pin@435||-45|0 Awire|net@1059|||0|pin@435||-45|0|wire90@51|b|-46.5|0 Awire|net@1060|||0|inv@32|in|-52|12|pin@436||-54|12 Awire|net@1061|||0|wire90@39|a|-49|24|pin@437||-54|24 Awire|net@1062|||2700|pin@436||-54|12|pin@437||-54|24 -Awire|net@1066|||900|conn@6|y|-60|31|pin@439||-60|28 -Awire|net@1070|||900|pin@439||-60|28|pin@364||-60|8 -Awire|net@1072|||0|predDri2@3|mc|9|28|pin@439||-60|28 -Awire|net@1073|||900|inv@33|in|0|3|pin@372||0|0 -Awire|net@1076|||1800|pin@441||0|12|invI@10|in|4|12 -Awire|net@1077|||1800|wire90@41|b|-3.5|12|pin@441||0|12 -Awire|net@1078|||900|invI@9|in|0|15.5|pin@441||0|12 -Awire|net@1079|||1800|invI@11|in|-37|12|pin@431||-36|12 -Awire|net@1080|||900|inv@34|in|-36|2|pin@383||-36|0 +Awire|net@1080|||900|inv@34|in|-30|2|pin@383||-30|0 +Awire|net@1083|||900|conn@6|y|-60|31|pin@364||-60|8 +Awire|net@1084|||0|conn@16|y|0.5|12|pin@374||-5|12 +Awire|net@1085|||900|invI@11|in|-18|15.5|pin@380||-18|12 Edo[Ld,Co,reD]|do[ins]|D4G2;|conn@7|a|I -Emc_1|do[reD]|D4G2;|conn@16|a|I +Emc_1|doneLO[M]|D4G2;|conn@16|a|I Es[4:6]|fire[zz]|D6G2;|conn@14|y|O Emc||D4G2;|conn@6|a|I Eolc[load,dec]|olc[load]|D6G2;|conn@9|y|O @@ -4885,7 +4844,7 @@ Eload[1]|load[T]|D4G2;|conn@7|a|I X # Cell olcWcont;1{ic} -ColcWcont;1{ic}||artwork|1237031259178|1240677267290|E +ColcWcont;1{ic}||artwork|1237031259178|1241048438835|E Ngeneric:Facet-Center|art@0||0|0||||AV Nschematic:Bus_Pin|pin@2||-5|0|-1|-1|| Ngeneric:Invisible-Pin|pin@3||-4|0|1|1|| @@ -4944,7 +4903,7 @@ AThicker|net@28|||FS1800|pin@38||4|1|pin@39||5|1 AThicker|net@29|||FS900|pin@38||4|1|pin@19||4|-6 AThicker|net@32|||FS900|pin@36||-4|5|pin@16||-4|-6 Edo[ins]||D5G2;|pin@35||I -EDvoid_1|do[reD]|D5G2;|pin@34||I +EDvoid_1|doneLO[M]|D5G2;|pin@34||I Eflag[D][set,clr]||D5G2;|pin@4||O Eilc[load]||D5G2;|pin@6||O EinLO[1:6]||D5G2;|pin@8||I @@ -5203,7 +5162,7 @@ Evdd_77||D5G5;|loadORco@0|vdd_18|P X # Cell olcWcont;2{sch} -ColcWcont;2{sch}||schematic|1236866624132|1240677267290| +ColcWcont;2{sch}||schematic|1236866624132|1241048438835| Ngeneric:Facet-Center|art@0||0|0||||AV NOff-Page|conn@1||0|-40|||YRRR| NOff-Page|conn@4||-13|-3|||Y| @@ -5328,7 +5287,7 @@ Abus|p2p,p1p,rd|D5G2;|-0.5|IJ900|scanEx3h@2|p2p,p1p,rd|55|-3|pin@30||55|-7 Abus|s[1:2]|D5G2;|-0.5|IJ2700|loadORco@0|s[1:2]|4|6|pin@60||4|10 Abus|s[1:2]|D5G2;|-0.5|IJ2700|scanEx2h@0|dIn[1:3]|72|3|pin@63||72|8 Edo[ins]||D4G2;|conn@13|a|I -EDvoid_1|do[reD]|D4G2;|conn@12|a|I +EDvoid_1|doneLO[M]|D4G2;|conn@12|a|I Eflag[D][set,clr]||D6G2;|conn@7|y|O Eilc[load]||D6G2;|conn@6|y|O EinLO[1:6]||D4G2;|conn@1|a|I diff --git a/electric/moveM.jelib b/electric/moveM.jelib index b4d2a92..5e20fa6 100755 --- a/electric/moveM.jelib +++ b/electric/moveM.jelib @@ -159,7 +159,7 @@ Eflag[D][set]||D6G2;|conn@7|y|O X # Cell ilcMoveOut;1{ic} -CilcMoveOut;1{ic}||artwork|1236743723435|1240671853463|EI +CilcMoveOut;1{ic}||artwork|1236743723435|1241048384054|EI Ngeneric:Facet-Center|art@0||0|0||||AV Nschematic:Bus_Pin|pin@0||-11|-7|-1|-1|R| Ngeneric:Invisible-Pin|pin@1||-11|-6|1|1|R| @@ -238,7 +238,7 @@ AThicker|net@43|||FS1800|pin@58||0|5|pin@59||1|5 AThicker|net@44|||FS2700|pin@24||-12|-2|pin@61||-12|5 AThicker|net@45|||FS0|pin@61||-12|5|pin@62||-13|5 Edo[Mv,Tp]|do[ins]|D5G2;|pin@2||I -Edo[reD]||D5G2;|pin@32||O +Edo[reD]|doneLO[M]|D5G2;|pin@32||O Etorp|epi[torp]|D5G2;|pin@14||I Efire[M]||D5G2;|pin@4||O Eflag[D][set]||D5G2;|pin@34||O @@ -529,7 +529,7 @@ Evdd_64||D5G2;|pinsVddG@2|vdd_1|P X # Cell ilcMoveOut;2{sch} -CilcMoveOut;2{sch}||schematic|1236742999975|1240848440230| +CilcMoveOut;2{sch}||schematic|1236742999975|1241048384054| Ngeneric:Facet-Center|art@0||0|0||||AV NOff-Page|conn@0||2|4|||RRR| NOff-Page|conn@1||-8.5|13|||XYRR| @@ -671,7 +671,7 @@ Abus|s[1:2]|D5G2;|-0.5|IJ2700|scanEx2h@0|dIn[1:3]|65|3|pin@69||65|11 Abus|s[1:3]|D5G2;|-0.5|IJ2700|outDockM@0|s[1:5]|2|21|pin@36||2|27 Awire|s[3]|D5G2;||2700|scanEx1h@0|dIn[1:2]|72|3|pin@72||72|10 Edo[Mv,Tp]|do[ins]|D4G2;|conn@6|a|I -Edo[reD]||D6G2;|conn@10|y|O +Edo[reD]|doneLO[M]|D6G2;|conn@10|y|O Eepi[torp]||D4G2;|conn@1|a|I Efire[M]||D6G2;|conn@0|y|O Eflag[D][set]||D6G2;|conn@11|y|O @@ -844,7 +844,7 @@ Efire[T_1]|winLO[M]|D4G2;|conn@3|a|I X # Cell moveOut;1{ic} -CmoveOut;1{ic}||artwork|1231680916842|1240746537490|EI +CmoveOut;1{ic}||artwork|1231680916842|1241048211391|EI Ngeneric:Facet-Center|art@0||0|0||||AV NThick-Circle|art@1||3.5|0|1|1|| Nschematic:Bus_Pin|pin@0||-4|0|-1|-1|| @@ -905,7 +905,7 @@ AThicker|net@52|||FS2700|pin@54||3|-5|pin@64||3|3 AThicker|net@53|||FS2700|pin@29||-3|-2|pin@71||-3|0 AThicker|net@54|||FS0|pin@71||-3|0|pin@72||-4|0 Edo[Mv,Tp]|do[ins]|D5G2;|pin@0||I -Edo[reD]||D5G2;|pin@51||O +Edo[reD]|doneLO[M]|D5G2;|pin@51||O Etorp|epi[torp]|D5G2;|pin@14||I Efire[M]||D5G2;|pin@45||O Eflag[D][set]||D5G2;|pin@53||O @@ -1085,7 +1085,7 @@ EsinLO[M]|winLO[M]|D5G2;|pin@185||O X # Cell moveOut;3{sch} -CmoveOut;3{sch}||schematic|1236301496751|1241026330491| +CmoveOut;3{sch}||schematic|1236301496751|1241050030932| Ngeneric:Facet-Center|art@0||0|0||||AV NOff-Page|conn@1||6|36|||YR| NOff-Page|conn@3||-19|2|||Y| @@ -1094,7 +1094,7 @@ NOff-Page|conn@8||60.5|25.5|||RR| NOff-Page|conn@9||-19|-7|||| NOff-Page|conn@15||-16|-2|||Y| NOff-Page|conn@17||-14|4|||Y| -NOff-Page|conn@19||38|-54|||| +NOff-Page|conn@19||32|-53|||| NOff-Page|conn@20||47|-34|||| NOff-Page|conn@25||9|42|||YRR| NOff-Page|conn@29||24|48|||YRRR| @@ -1104,6 +1104,7 @@ IredFive:inv;1{ic}|inv@10||39|43|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X( IredFive:inv;1{ic}|inv@13||-11|30|YRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:inv;1{ic}|inv@14||-11|18|YRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:inv;1{ic}|inv@15||-11|-18|YRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 +IredFive:inv;1{ic}|inv@16||17.5|-53|XYRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:invI;2{ic}|invI@9||-23|30|YRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:invI;2{ic}|invI@10||-23|18|YRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IredFive:invI;2{ic}|invI@11||-23|-18|YRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 @@ -1153,11 +1154,11 @@ NWire_Pin|pin@123||24|31|||| NWire_Pin|pin@128||24|-43|||X| NWire_Pin|pin@132||24|-41|||| NWire_Pin|pin@133||24|-46|||| -NWire_Pin|pin@134||12|-54|||| +NWire_Pin|pin@134||12|-53|||| NWire_Pin|pin@135||24|3|||| NWire_Pin|pin@136||48|14|||| NBus_Pin|pin@149||-10|-4|-1|-1|| -Ngeneric:Invisible-Pin|pin@151||-0.5|56|||||ART_message(D5G3;)Sies 26 April 2009 +Ngeneric:Invisible-Pin|pin@151||-0.5|56|||||ART_message(D5G3;)Sies 29 April 2009 NBus_Pin|pin@152||-10|-7|-1|-1|| NWire_Pin|pin@154||-6|-40|||| NWire_Pin|pin@155||-6|-28|||| @@ -1169,7 +1170,6 @@ IdriversM:predDri20wMC;1{ic}|predDri2@3||0|18|YRR||D5G4; IdriversM:predDri20wMC;1{ic}|predDri2@4||0|30|YRR||D5G4; IdriversM:predDri40;1{ic}|predDri4@0||0|-42|X||D5G4; IdriversM:predDri40;1{ic}|predDri4@1||0|-30|X||D5G4; -IdriversM:sucDri20;1{ic}|sucDri20@0||20|-54|||D5G4; IorangeTSMC090nm:wire90;1{ic}|wire90@9||30|19|||D0G4;|ATTR_L(D5G1;PUD)D362.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@10||30.5|43|||D0G4;|ATTR_L(D5G1;PUD)D602.6999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@11||10|32|||D0G4;|ATTR_L(D5G1;PUD)D269.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 @@ -1179,7 +1179,6 @@ IorangeTSMC090nm:wire90;1{ic}|wire90@15||7|-42|||D0G4;|ATTR_L(D5G1;PUD)D709.6|AT IorangeTSMC090nm:wire90;1{ic}|wire90@16||7|-30|||D0G4;|ATTR_L(D5G1;PUD)D269.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@17||35|-30|||D0G4;|ATTR_L(D5G1;PUD)D269.90000000000003|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 Awire|do[ins]|D5G2;||2700|pin@154||-6|-40|pin@155||-6|-28 -Awire|done[M]|D5G2;||2700|pin@134||12|-54|pin@159||12|-42 Awire|fire[T]|D5G2;||900|pin@17||12|-3|pin@13||12|-16 Awire|ilc[do]|D5G2;||900|pin@117||48|20|pin@136||48|14 Awire|ilc[mo]|D5G2;||900|pin@128||24|-43|pin@133||24|-46 @@ -1195,7 +1194,6 @@ Awire|net@35|||2700|pin@20||-6|-18|pin@21||-6|2 Awire|net@47|||0|pin@21||-6|2|conn@3|y|-17|2 Abus|net@128||-0.5|IJ1800|pin@149||-10|-4|moveRepe@0|bit[Di,Ti]|-3|-4 Abus|net@141||-0.5|IJ0|moveRepe@0|in[D,T]|-3|-2|conn@15|y|-14|-2 -Awire|net@178|||1800|sucDri20@0|succ|24|-54|conn@19|a|36|-54 Awire|net@179|||900|pms1@0|d|43|-32|pin@100||43|-34 Awire|net@180|||0|conn@20|a|45|-34|pin@100||43|-34 Awire|net@191|||0|predDri2@3|pred|-3|18|pin@105||-6|18 @@ -1236,7 +1234,6 @@ Awire|net@228|||2700|pin@10||6|-20|pin@115||6|16 Awire|net@240|||1800|nor2n@1|ina|20.5|-43|pin@128||24|-43 Awire|net@250|||1800|pin@159||12|-42|nor2n@1|out|15.5|-42 Awire|net@251|||1800|nor2n@1|inb|20.5|-41|pin@132||24|-41 -Awire|net@256|||1800|pin@134||12|-54|sucDri20@0|in|16|-54 Awire|net@258|||900|conn@1|y|6|34|pin@116||6|28 Awire|net@260|||900|pin@135||24|3|pin@132||24|-41 Awire|net@262|||1800|moveRepe@0|winLO[M]|3|3|pin@135||24|3 @@ -1256,6 +1253,9 @@ Awire|net@341|||0|pin@156||12|-30|wire90@16|b|9.5|-30 Awire|net@342|||900|pin@13||12|-16|pin@156||12|-30 Awire|net@345|||1800|predDri4@0|in|2|-42|wire90@15|a|4.5|-42 Awire|net@346|||1800|wire90@15|b|9.5|-42|pin@159||12|-42 +Awire|net@348|||2700|pin@134||12|-53|pin@159||12|-42 +Awire|net@349|||1800|pin@134||12|-53|inv@16|in|15|-53 +Awire|net@350|||1800|inv@16|out|20|-53|conn@19|a|30|-53 Awire|pred[D]|D5G2;||900|pin@105||-6|18|pin@111||-6|13 Awire|pred[T]|D5G2;||900|pin@108||-6|30|pin@112||-6|25.5 Awire|s[1]|D5G2;||2700|pin@109||-29|30|pin@110||-29|36 @@ -1264,7 +1264,7 @@ Awire|s[3]|D5G2;||2700|pin@4||-29|-18|pin@5||-29|-12 Awire|sel[Di]|D5G2;||900|pin@121||45|18|pin@119||45|14 Awire|sel[Ti]|D5G2;||2700|pin@120||45|34|pin@118||45|38 Edo[Mv,Tp]|do[ins]|D4G2;|conn@17|a|I -Edo[reD]||D6G2;|conn@19|y|O +Edo[reD]|doneLO[M]|D6G2;|conn@19|y|O Eepi[torp]||D4G2;|conn@3|a|I Efire[M]||D6G2;|conn@25|y|O Eflag[D][set]||D6G2;|conn@20|y|O diff --git a/electric/predicateM.jelib b/electric/predicateM.jelib index b6d4e71..cbe7094 100755 --- a/electric/predicateM.jelib +++ b/electric/predicateM.jelib @@ -701,14 +701,14 @@ Evdd_34||D5G2;|scanEx3h@0|vdd_3|P X # Cell ohPredAll;3{sch} -CohPredAll;3{sch}||schematic|1231960520598|1241033920871| +CohPredAll;3{sch}||schematic|1231960520598|1241047864126| Ngeneric:Facet-Center|art@0||0|0||||AV IwiresL:bitAssignments;1{ic}|bitAssig@0||-37.5|11.5||V|D5G4; NOff-Page|conn@0||26.5|30|||| NOff-Page|conn@1||26.5|27|||| NOff-Page|conn@2||-24|24|||| NOff-Page|conn@9||-23|-30|||| -NOff-Page|conn@11||-4|30|||| +NOff-Page|conn@11||-7|30|||| NOff-Page|conn@16||-39|-19|||YRRR| NOff-Page|conn@17||-26.5|-9|||| NOff-Page|conn@18||-42.5|-9|||Y| @@ -722,7 +722,7 @@ IredFive:nand2n_sy;1{ic}|nand2n_s@0||15|0|RRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2.5; Inand3in20sr;1{ic}|nand3in2@1||24|0|R||D5G4; IredFive:nor2n_sy;1{ic}|nor2n_sy@0||40|-6|X||D0G4;|ATTR_Delay(D5G1;NPX3;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX2.25;Y2.25;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1 IohPredAll;1{ic}|ohPredAl@1||-25|40|||D5G4; -IohPredDo;1{ic}|ohPredDo@1||9|27|||D5G4; +IohPredDo;1{ic}|ohPredDo@1||6|27|||D5G4; IohPredPred;1{ic}|ohPredPr@1||-4|-27|||D5G4; Ngeneric:Invisible-Pin|pin@0||2.5|48|||||ART_message(D5G5;)SohPredAll Ngeneric:Invisible-Pin|pin@1||3|44|||||ART_message(D5G3;)Sies 25 April 2009 @@ -748,12 +748,12 @@ NWire_Pin|pin@52||45|-7|||| NWire_Pin|pin@53||45|-10|||| NWire_Pin|pin@64||3|-12|||| NWire_Pin|pin@66||-12|18|||| -NWire_Pin|pin@67||5|18|||| -NWire_Pin|pin@68||13|18|||| +NWire_Pin|pin@67||2|18|||| +NWire_Pin|pin@68||10|18|||| NWire_Pin|pin@69||24|18|||| NWire_Pin|pin@70||15|-27|||| NBus_Pin|pin@74||-8|-17|-1|-1|| -NWire_Pin|pin@75||4|36|||| +NWire_Pin|pin@75||1|36|||| NWire_Pin|pin@91||45|-12|||| NWire_Pin|pin@92||45|-16.5|||| NBus_Pin|pin@93||-33|2|-1|-1|| @@ -771,22 +771,23 @@ IorangeTSMC090nm:wire90;1{ic}|wire90@3||4|-9|X||D0G4;|ATTR_L(D5G1;PUD)D355.30000 IorangeTSMC090nm:wire90;1{ic}|wire90@4||20|6|X||D0G4;|ATTR_L(D5G1;PUD)D1035.5|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@5||-5.5|6|X||D0G4;|ATTR_L(D5G1;PUD)D602.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@6||-8.5|-9|X||D0G4;|ATTR_L(D5G1;PUD)D613.9|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@7||-0.5|18|X||D0G4;|ATTR_L(D5G1;PUD)D782.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 +IorangeTSMC090nm:wire90;1{ic}|wire90@7||-6|18|X||D0G4;|ATTR_L(D5G1;PUD)D782.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@9||10|-27|X||D0G4;|ATTR_L(D5G1;PUD)D2516.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@10||30|36|||D0G4;|ATTR_L(D5G1;PUD)D215.39999999999998|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -IorangeTSMC090nm:wire90;1{ic}|wire90@11||18.5|18|X||D0G4;|ATTR_L(D5G1;PUD)D782.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 +IorangeTSMC090nm:wire90;1{ic}|wire90@11||18|18|X||D0G4;|ATTR_L(D5G1;PUD)D782.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 Awire|do[ins]|D5G2;||900|pin@91||45|-12|pin@92||45|-16.5 Awire|fire[both]|D5G2;||900|nand2n_s@0|out|15|-2.5|pin@70||15|-27 -Awire|fire[skip]|D5G2;||900|pin@66||-12|18|invI@1|out|-12|14.5 +Awire|fire[do]|D5G2;||900|ohPredDo@1|hit[do]|10|22|pin@68||10|18 +Awire|fire[skip]|D5G2;||2700|pin@67||2|18|ohPredDo@1|hit[skip]|2|22 Awire|mc|D5G2;||2700|ohPredPr@1|mc|-11|-22|pin@46||-11|-19 -Awire|mc|D5G2;||2700|ohPredDo@1|mc|4|32|pin@75||4|36 +Awire|mc|D5G2;||2700|ohPredDo@1|mc|1|32|pin@75||1|36 Awire|mc|D5G2;||2700|scanEx3h@0|mc|-37|-5|pin@94||-37|-3 Awire|net@11|||2700|pin@7||-11|-6|nand2_sy@0|inb|-11|-1.5 Awire|net@19|||2700|ohPredPr@1|resetLO|0|-22|pin@13||0|-9 Awire|net@21|||2700|pin@14||18|-9|pin@15||18|-0.5 Abus|net@23||-0.5|IJ0|ohPredPr@1|flag[A,B][set,clr]|-13|-24|pin@17||-18|-24 Abus|net@24||-0.5|IJ2700|pin@17||-18|-24|pin@18||-18|24 -Abus|net@25||-0.5|IJ1800|pin@18||-18|24|ohPredDo@1|flag[A,B][set,clr]|2|24 +Abus|net@25||-0.5|IJ1800|pin@18||-18|24|ohPredDo@1|flag[A,B][set,clr]|-1|24 Awire|net@35|||0|pin@24||26|-6|pin@7||-11|-6 Awire|net@37|||900|nand3in2@1|inC|26|-2.5|pin@24||26|-6 Awire|net@39|||0|nor2n_sy@0|out|37.5|-6|wire90@0|a|34.5|-6 @@ -798,7 +799,7 @@ Awire|net@50|||0|pin@27||22|-12|wire90@2|a|9|-12 Awire|net@52|||1800|wire90@3|a|6.5|-9|pin@14||18|-9 Awire|net@53|||0|wire90@3|b|1.5|-9|pin@13||0|-9 Awire|net@57|||1800|pin@15||18|-0.5|nand3in2@1|resetLO|20|-0.5 -Abus|net@58||-0.5|IJ1800|ohPredDo@1|succ[skip,do]|16|27|conn@1|a|24.5|27 +Abus|net@58||-0.5|IJ1800|ohPredDo@1|succ[skip,do]|13|27|conn@1|a|24.5|27 Abus|net@62||-0.5|IJ1800|conn@2|y|-22|24|pin@18||-18|24 Awire|net@63|||2700|nand2_sy@0|out|-12|3.5|pin@29||-12|6 Awire|net@64|||1800|pin@29||-12|6|wire90@5|b|-8|6 @@ -812,22 +813,20 @@ Awire|net@95|||2700|pin@45||-13|-9|nand2_sy@0|ina|-13|-1.5 Awire|net@104|||1800|nor2n_sy@0|inb|42.5|-5|pin@50||45|-5 Awire|net@106|||1800|nor2n_sy@0|ina|42.5|-7|pin@52||45|-7 Abus|net@119||-0.5|IJ1800|conn@9|y|-21|-30|ohPredPr@1|m1cate[1:6][T,F]|-13|-30 -Abus|net@126||-0.5|IJ1800|conn@11|y|-2|30|ohPredDo@1|sel[Fl,Lo,Co,Tp,Mv,Lt,Cd]|2|30 +Abus|net@126||-0.5|IJ1800|conn@11|y|-5|30|ohPredDo@1|sel[Fl,Lo,Co,Tp,Mv,Lt,Cd]|-1|30 Awire|net@139|||0|wire90@2|b|4|-12|pin@64||3|-12 Awire|net@140|||900|pin@64||3|-12|ohPredPr@1|do|3|-22 -Awire|net@144|||0|wire90@7|b|-3|18|pin@66||-12|18 +Awire|net@144|||0|wire90@7|b|-8.5|18|pin@66||-12|18 Awire|net@146|||900|invI@0|in|24|9.5|pin@40||24|6 Awire|net@147|||1800|wire90@5|a|-3|6|pin@30||14|6 Awire|net@148|||900|invI@1|in|-12|9.5|pin@29||-12|6 -Awire|net@149|||1800|wire90@7|a|2|18|pin@67||5|18 -Awire|net@150|||2700|pin@67||5|18|ohPredDo@1|hit[skip]|5|22 -Awire|net@151|||900|ohPredDo@1|hit[do]|13|22|pin@68||13|18 +Awire|net@149|||1800|wire90@7|a|-3.5|18|pin@67||2|18 Awire|net@158|||900|pin@30||14|6|nand2n_s@0|ina|14|2.5 Awire|net@159|||900|pin@41||16|6|nand2n_s@0|inb|16|2.5 Awire|net@160|||0|wire90@9|b|7.5|-27|ohPredPr@1|hit[do]|5|-27 Awire|net@161|||1800|wire90@9|a|12.5|-27|pin@70||15|-27 Awire|net@166|||900|pin@69||24|18|invI@0|out|24|14.5 -Awire|net@191|||0|pin@99||18|30|ohPredDo@1|do[Lo,Co,Tp,Mv,Lt]|16|30 +Awire|net@191|||0|pin@99||18|30|ohPredDo@1|do[Lo,Co,Tp,Mv,Lt]|13|30 Awire|net@193|||1800|wire90@1|a|32|-12|invI@2|out|36.5|-12 Awire|net@194|||1800|invI@2|in|41.5|-12|pin@91||45|-12 Awire|net@197|||0|scanEx3h@0|sin|-37|-9|conn@18|y|-40.5|-9 @@ -838,8 +837,9 @@ Awire|net@202|||0|conn@0|a|24.5|30|pin@99||18|30 Awire|net@203|||900|pin@98||18|36|pin@99||18|30 Awire|net@205|||0|inv@1|in|20|36|pin@98||18|36 Awire|net@206|||0|wire90@10|a|27.5|36|inv@1|out|25|36 -Awire|net@207|||0|wire90@11|b|16|18|pin@68||13|18 -Awire|net@208|||1800|wire90@11|a|21|18|pin@69||24|18 +Awire|net@207|||0|wire90@11|b|15.5|18|pin@68||10|18 +Awire|net@208|||1800|wire90@11|a|20.5|18|pin@69||24|18 +Awire|net@209|||900|pin@66||-12|18|invI@1|out|-12|14.5 Abus|p2p,p1p,rd|D5G2;|-0.5|IJ900|scanEx3h@0|p2p,p1p,rd|-35|-12|pin@95||-35|-16.5 Awire|ps[do]|D5G2;||2700|pin@50||45|-5|pin@51||45|-2 Awire|ps[skip]|D5G2;||900|pin@52||45|-7|pin@53||45|-10 diff --git a/electric/stagesM.jelib b/electric/stagesM.jelib index 1cbdf3f..5045046 100755 --- a/electric/stagesM.jelib +++ b/electric/stagesM.jelib @@ -1,5 +1,5 @@ # header information: -HstagesM|8.09a +HstagesM|8.08k # Views: Vicon|ic @@ -6472,7 +6472,7 @@ Evdd_65|vdd_37|D5G7;|cover7hN@0|vdd_63|P X # Cell outDockCenter;3{sch} -CoutDockCenter;3{sch}||schematic|1233272314089|1240866705467| +CoutDockCenter;3{sch}||schematic|1233272314089|1241136320276| Ngeneric:Facet-Center|art@0||0|0||||AV IwiresL:bitAssignments;1{ic}|bitAssig@0||-62|29|||D5G4; NOff-Page|conn@0||23|-20.5|||RRR| @@ -6568,8 +6568,8 @@ IorangeTSMC090nm:wire90;1{ic}|wire90@9||-28|23|||D0G4;|ATTR_L(D5G1;PUD)S1850|ATT IorangeTSMC090nm:wire90;1{ic}|wire90@10||-28|17|||D0G4;|ATTR_L(D5G1;PUD)S1852|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@24||-61|-1|||D0G4;|ATTR_L(D5G1;PUD)D867.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 IorangeTSMC090nm:wire90;1{ic}|wire90@25||30|-11|||D0G4;|ATTR_L(D5G1;PUD)D867.8|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3 -Awire|do[reD]|D5G2;||2700|pin@114||36|-16.5|pin@120||36|-11 -Awire|do[reD]|D5G2;||900|pin@186||-62|-5|pin@187||-62|-8 +Awire|doneLO[M]|D5G2;||900|pin@186||-62|-5|pin@187||-62|-8 +Awire|doneLO[M]|D5G2;||2700|pin@114||36|-16.5|pin@120||36|-11 Abus|flag[A,B,D][set,clr]|D5G2;|-0.5|IJ900|pin@126||-37|-9|pin@127||-37|-14 Abus|flag[A,B][set,clr]|D5G2;|-0.5|IJ900|pin@29||-101|-4|pin@30||-101|-7 Awire|flag[A][clr]|D5G2;||2700|pin@42||-46|17|pin@43||-46|20 diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java index 3f44de6..f7bc75d 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java +++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java @@ -1992,7 +1992,6 @@ public class MarinaTest { doOneTest(4); doOneTest(5); doOneTest(6); - doOneTest(1000); doOneTest(1001); doOneTest(1003); @@ -2005,7 +2004,6 @@ public class MarinaTest { doOneTest(3011); doOneTest(3012); doOneTest(3013); - doOneTest(3014); doOneTest(3015); doOneTest(3019); diff --git a/testCode/marina.spi b/testCode/marina.spi index 38ce8ee..8d466f1 100644 --- a/testCode/marina.spi +++ b/testCode/marina.spi @@ -1,7 +1,7 @@ *** SPICE deck for cell marinaOut{sch} from library aMarinaM *** Created on Mon Nov 17, 2008 08:47:24 *** Last revised on Mon Mar 30, 2009 06:59:15 -*** Written on Tue Apr 28, 2009 10:46:28 by Electric VLSI Design System, +*** Written on Thu Apr 30, 2009 17:07:37 by Electric VLSI Design System, *version 8.08k *** Layout tech: cmos90, foundry TSMC *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF @@ -833,7 +833,7 @@ Rres@3 net@8 net@11 8.07 Xwire@0 a b wire-C_0_011f-698_4-R_34_667m .ENDS wire90-698_4-layer_1-width_3 -*** CELL: driversL:dataDriver60{sch} +*** CELL: driversM:dataDriver60{sch} .SUBCKT dataDriver60 inA inB out Xinv@0 net@8 out inv-X_60 Xnand2@1 inA inB net@7 nand2-X_20 @@ -869,14 +869,14 @@ Rres@3 net@8 net@11 2.815 Xwire@0 a b wire-C_0_011f-243_6-R_34_667m .ENDS wire90-243_6-layer_1-width_3 -*** CELL: driversJ:predDri60wMC{sch} -.SUBCKT driversJ__predDri60wMC in mc pred +*** CELL: driversM:predDri60wMC{sch} +.SUBCKT predDri60wMC in mc pred XNMOSx@0 pred in gnd NMOSx-X_60 XNMOSx@1 pred mc gnd NMOSx-X_10 Xinv@0 pred net@145 inv-X_10 Xpms3@0 pred mc in net@174 pms3-X_3_333 Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3 -.ENDS driversJ__predDri60wMC +.ENDS predDri60wMC *** CELL: orangeTSMC090nm:NMOSx{sch} .SUBCKT NMOSx-X_16 d g s @@ -922,7 +922,7 @@ Rres@3 net@8 net@11 1.441 Xwire@0 a b wire-C_0_011f-124_7-R_34_667m .ENDS wire90-124_7-layer_1-width_3 -*** CELL: driversL:sucANDdri60{sch} +*** CELL: driversM:sucANDdri60{sch} .SUBCKT sucANDdri60 inA inB succ XPMOSx@0 succ net@51 vdd PMOSx-X_60 Xinv@0 succ net@71 inv-X_5 @@ -1046,7 +1046,7 @@ Xinv@4 pred net@472 inv-X_5 Xinv@5 silent net@463 inv-X_10 XinvI@0 net@357 net@409 inv-X_10 XinvI@1 net@475 s[1] inv-X_10 -XpredDri6@0 fire clear pred driversJ__predDri60wMC +XpredDri6@1 fire clear pred predDri60wMC XsucANDdr@4 net@499 fire succ sucANDdri60 Xtc[1] tranCap Xtc[2] tranCap @@ -1546,22 +1546,13 @@ Rres@3 net@8 net@11 6.289 Xwire@0 a b wire-C_0_011f-544_2-R_34_667m .ENDS wire90-544_2-layer_1-width_3 -*** CELL: driversJ:latchDriver60{sch} +*** CELL: driversM:latchDriver60{sch} .SUBCKT latchDriver60 in out Xinv@1 in net@16 inv-X_20 XinvI@2 net@17 out inv-X_60 Xwire90@0 net@16 net@17 wire90-544_2-layer_1-width_3 .ENDS latchDriver60 -*** CELL: driversL:predDri60wMC{sch} -.SUBCKT driversL__predDri60wMC in mc pred -XNMOSx@0 pred in gnd NMOSx-X_60 -XNMOSx@1 pred mc gnd NMOSx-X_10 -Xinv@0 pred net@145 inv-X_10 -Xpms3@0 pred mc in net@174 pms3-X_3_333 -Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3 -.ENDS driversL__predDri60wMC - *** CELL: redFive:pms2{sch} .SUBCKT pms2-X_10 d g g2 XPMOS@0 net@2 g vdd PMOSx-X_20 @@ -1613,7 +1604,7 @@ Rres@3 net@8 net@11 2.415 Xwire@0 a b wire-C_0_011f-209-R_34_667m .ENDS wire90-209-layer_1-width_3 -*** CELL: driversJ:sucORdri60{sch} +*** CELL: driversM:sucORdri60{sch} .SUBCKT sucORdri60 inA inB succ XPMOSx@0 succ net@51 vdd PMOSx-X_60 Xinv@0 succ net@71 inv-X_5 @@ -1650,9 +1641,9 @@ Xinv@0 pred net@533 inv-X_5 Xinv@1 fill net@537 inv-X_5 XinvI@0 net@454 s[1] inv-X_10 XinvI@1 net@602 s[2] inv-X_10 -XlatchDri@0 fire take latchDriver60 -XpredDri6@2 fire si[9] pred driversL__predDri60wMC -XsucORdri@1 fire net@320 succ sucORdri60 +XlatchDri@1 fire take latchDriver60 +XpredDri6@2 fire si[9] pred predDri60wMC +XsucORdri@2 fire net@320 succ sucORdri60 Xtc[1] tranCap Xtc[2] tranCap Xwire90@1 net@537 net@602 wire90-602_3-layer_1-width_3 @@ -2068,7 +2059,7 @@ Rres@3 net@8 net@11 1.233 Xwire@0 a b wire-C_0_011f-106_7-R_34_667m .ENDS wire90-106_7-layer_1-width_3 -*** CELL: driversL:predDri20wMC{sch} +*** CELL: driversM:predDri20wMC{sch} .SUBCKT predDri20wMC in mc pred XNMOSx@0 pred in gnd NMOSx-X_20 XNMOSx@1 pred mc gnd NMOSx-X_4 @@ -2116,7 +2107,7 @@ Rres@3 net@8 net@11 5.817 Xwire@0 a b wire-C_0_011f-503_4-R_34_667m .ENDS wire90-503_4-layer_1-width_3 -*** CELL: driversL:sucDri20{sch} +*** CELL: driversM:sucDri20{sch} .SUBCKT sucDri20 in succ Xinv@1 succ net@94 inv-X_4 Xinv@2 in net@110 inv-X_6 @@ -2639,7 +2630,7 @@ Xwire90@0 net@213 net@177 wire90-162_4-layer_1-width_3 Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3 .ENDS rsLatchA -*** CELL: driversL:sucORdri20{sch} +*** CELL: driversM:sucORdri20{sch} .SUBCKT sucORdri20 inA inB succ XPMOSx@0 succ net@51 vdd PMOSx-X_20 Xinv@0 succ net@71 inv-X_4 @@ -2867,8 +2858,8 @@ Xins2in20@0 take[A] take[B] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] +out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] +out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] +out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36 -XlatchDri@0 net@3 net@27 latchDriver60 -XlatchDri@1 net@7 net@23 latchDriver60 +XlatchDri@2 net@3 net@27 latchDriver60 +XlatchDri@3 net@7 net@23 latchDriver60 XscanEx3@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] +sir[7] sir[8] sor[1] scanEx3 Xtc[1] tranCap @@ -3160,8 +3151,8 @@ Xins1in20@1 net@25 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +outB[21] outB[22] outB[23] outB[24] outB[25] outB[26] outB[27] outB[28] +outB[29] outB[2] outB[30] outB[31] outB[32] outB[33] outB[34] outB[35] +outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] outB[8] outB[9] ins1in20Bx36 -XlatchDri@0 net@5 net@20 latchDriver60 -XlatchDri@1 net@6 net@22 latchDriver60 +XlatchDri@2 net@5 net@20 latchDriver60 +XlatchDri@3 net@6 net@22 latchDriver60 XscanEx2v@1 net@48[1] net@48[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] +sir[6] sir[7] sir[8] sor[1] scanEx2 Xtc[1] tranCap @@ -3274,7 +3265,7 @@ Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] +out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] +out[7] out[8] out[9] ins1in20Bx36 -XlatchDri@0 fire[1] take[1] latchDriver60 +XlatchDri@1 fire[1] take[1] latchDriver60 XscanEx1@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] +sir[8] sor[1] scanEx1 Xtc[1] tranCap @@ -3490,7 +3481,7 @@ Rres@3 net@8 net@11 1.328 Xwire@0 a b wire-C_0_011f-114_9-R_34_667m .ENDS wire90-114_9-layer_1-width_3 -*** CELL: driversL:suc3ANDdri20{sch} +*** CELL: driversM:suc3ANDdri20{sch} .SUBCKT suc3ANDdri20 inA inB inC succ XPMOSx@0 succ net@51 vdd PMOSx-X_20 Xinv@0 succ net@71 inv-X_4 @@ -3500,7 +3491,7 @@ Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3 Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3 .ENDS suc3ANDdri20 -*** CELL: driversL:sucANDdri20{sch} +*** CELL: driversM:sucANDdri20{sch} .SUBCKT sucANDdri20 inA inB succ XPMOSx@0 succ net@51 vdd PMOSx-X_20 Xinv@0 succ net@71 inv-X_4 @@ -3565,7 +3556,7 @@ Xins1in20@0 take[epi] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +epi[23] epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30] +epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6] +epi[7] epi[8] epi[9] ins1in20Bx36 -XlatchDri@0 net@0 take[epi] latchDriver60 +XlatchDri@1 net@0 take[epi] latchDriver60 XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] +sir[8] sor[1] scanEx1 XtranCap@0 tranCap @@ -3657,7 +3648,7 @@ Xins1in20@0 take[od] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] +od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25] +od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35] +od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] ins1in20Bx36 -XlatchDri@0 fire[1] take[od] latchDriver60 +XlatchDri@1 fire[1] take[od] latchDriver60 XonDeck@0 m1[29] m1[30] net@11 flag[A][clr] flag[A][set] flag[D][clr] +flag[D][set] sir[9] od[ABORT] od[HEAD] od[OTHER] do[od] net@62[1] net@62[0] +onDeck @@ -4093,8 +4084,8 @@ Xins2in20@0 take[E] take[P] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] +rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] +rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] +rq[7] rq[8] rq[9] ins2in20Ax36 -XlatchDri@0 net@3 take[E] latchDriver60 -XlatchDri@1 net@7 take[P] latchDriver60 +XlatchDri@2 net@3 take[E] latchDriver60 +XlatchDri@3 net@7 take[P] latchDriver60 XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD] +od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4] reQueue XscanEx1@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] @@ -4160,6 +4151,10 @@ XrqDockSt@0 epi[OTHER] epi[TAIL] net@45[26] net@45[25] net@45[24] net@45[23] +rqDockStage .ENDS epiRQod +*** CELL: wiresL:bitAssignments{sch} +.SUBCKT bitAssignments +.ENDS bitAssignments + *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-161_8-R_34_667m a b Ccap@0 gnd net@14 0.593f @@ -4185,22 +4180,19 @@ Xwire90@0 net@27 net@32 wire90-161_8-layer_1-width_3 Xwire90@1 net@24 net@9 wire90-372_8-layer_1-width_3 .ENDS ctrAND2in30A +*** CELL: driversM:predDri40{sch} +.SUBCKT predDri40 in pred +XNMOSx@0 pred in gnd NMOSx-X_40 +.ENDS predDri40 + *** CELL: gaspM:gaspLit{sch} -.SUBCKT gaspLit do[Lt] fire[L] mc ready s[1] +.SUBCKT gaspLit do[ins] fire[L] ready sel[Lt] XctrAND2i@0 net@189 ready fire[L] ctrAND2in30A -Xinv@1 do[Lt] net@190 inv-X_5 -XinvI@0 net@189 s[1] inv-X_10 -XpredDri2@1 fire[L] mc do[Lt] predDri20wMC -Xwire90@1 net@190 net@189 wire90-414-layer_1-width_3 +Xnand2@0 sel[Lt] do[ins] net@233 nand2-X_5 +XpredDri4@0 fire[L] do[ins] predDri40 +Xwire90@1 net@233 net@189 wire90-414-layer_1-width_3 .ENDS gaspLit -*** CELL: driversJ:latchAndDriver60{sch} -.SUBCKT latchAndDriver60 inA inB out -Xinv@0 net@8 out inv-X_60 -Xnand2@0 inA inB net@26 nand2-X_20 -Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3 -.ENDS latchAndDriver60 - *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-387_3-R_34_667m a b Ccap@0 gnd net@14 1.42f @@ -4217,13 +4209,20 @@ Rres@3 net@8 net@11 4.475 Xwire@0 a b wire-C_0_011f-387_3-R_34_667m .ENDS wire90-387_3-layer_1-width_3 -*** CELL: driversJ:latchAndDriver30{sch} +*** CELL: driversM:latchAndDriver30{sch} .SUBCKT latchAndDriver30 inA inB out Xinv@0 net@8 out inv-X_30 Xnand2@0 inA inB net@26 nand2-X_10 Xwire90@0 net@26 net@8 wire90-387_3-layer_1-width_3 .ENDS latchAndDriver30 +*** CELL: driversM:latchAndDriver60{sch} +.SUBCKT latchAndDriver60 inA inB out +Xinv@0 net@8 out inv-X_60 +Xnand2@0 inA inB net@26 nand2-X_20 +Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3 +.ENDS latchAndDriver60 + *** CELL: registersM:data2in60Cx18{sch} .SUBCKT data2in60Cx18 dcl[A] dcl[B] inA[10] inA[11] inA[12] inA[13] inA[14] +inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] @@ -4637,11 +4636,6 @@ Xwire90@5 fire[B] fire[B2] wire90-2330-layer_1-width_3 Xwire90@6 fire[A] fire[A2] wire90-2330-layer_1-width_3 .ENDS addr2in60Cx15 -*** CELL: gates3inM:nand3in6.6{sch} -.SUBCKT nand3in6_6 inA inB inC out -Xnand3@0 inA inB inC out nand3-X_6_667 -.ENDS nand3in6_6 - *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-3495_7-R_34_667m a b Ccap@0 gnd net@14 12.818f @@ -4722,6 +4716,22 @@ Rres@3 net@8 net@11 5.008 Xwire@0 a b wire-C_0_011f-433_4-R_34_667m .ENDS wire90-433_4-layer_1-width_3 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-425_6-R_34_667m a b +Ccap@0 gnd net@14 1.561f +Ccap@1 gnd net@8 1.561f +Ccap@2 gnd net@11 1.561f +Rres@0 net@14 a 2.459 +Rres@1 net@11 net@14 4.918 +Rres@2 b net@8 2.459 +Rres@3 net@8 net@11 4.918 +.ENDS wire-C_0_011f-425_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-425_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-425_6-R_34_667m +.ENDS wire90-425_6-layer_1-width_3 + *** CELL: registersM:newPathReg{sch} .SUBCKT newPathReg aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] +aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] @@ -4736,14 +4746,15 @@ Xaddr2in6@0 dp[10] dp[11] dp[12] dp[12] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] Xinv@1 ps[13] net@46 inv-X_10 Xinv@2 ps[14] net@47 inv-X_10 Xinv@3 ps[15] net@52 inv-X_10 -XinvI@0 net@19 net@40 inv-X_30 -XlatchAnd@0 ps[14] fire[M] net@43 latchAndDriver30 -Xnand3in6@1 net@25 net@28 fire[M] net@19 nand3in6_6 +XinvI@0 net@58 net@40 inv-X_30 +XlatchAnd@1 ps[14] fire[M] net@43 latchAndDriver30 +Xnand3@1 net@25 net@28 fire[M] net@59 nand3-X_6_667 Xwire90@0 net@43 take[ps] wire90-3495_7-layer_1-width_3 Xwire90@1 net@40 take[dp] wire90-3616_3-layer_1-width_3 Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3 Xwire90@4 net@47 net@25 wire90-358-layer_1-width_3 Xwire90@5 net@52 ps[15not] wire90-433_4-layer_1-width_3 +Xwire90@6 net@59 net@58 wire90-425_6-layer_1-width_3 .ENDS newPathReg *** CELL: redFive:nor2_sy{sch} @@ -4758,8 +4769,72 @@ Xpms2_sy@0 out ina inb pms2_sy-X_10 Xnor2@0 ina inb out nor2_sy-X_10 .ENDS nor2n_sy-X_10 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-632_9-R_34_667m a b +Ccap@0 gnd net@14 2.321f +Ccap@1 gnd net@8 2.321f +Ccap@2 gnd net@11 2.321f +Rres@0 net@14 a 3.657 +Rres@1 net@11 net@14 7.314 +Rres@2 b net@8 3.657 +Rres@3 net@8 net@11 7.314 +.ENDS wire-C_0_011f-632_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-632_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-632_9-R_34_667m +.ENDS wire90-632_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-402-R_34_667m a b +Ccap@0 gnd net@14 1.474f +Ccap@1 gnd net@8 1.474f +Ccap@2 gnd net@11 1.474f +Rres@0 net@14 a 2.323 +Rres@1 net@11 net@14 4.645 +Rres@2 b net@8 2.323 +Rres@3 net@8 net@11 4.645 +.ENDS wire-C_0_011f-402-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-402-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-402-R_34_667m +.ENDS wire90-402-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-419_5-R_34_667m a b +Ccap@0 gnd net@14 1.538f +Ccap@1 gnd net@8 1.538f +Ccap@2 gnd net@11 1.538f +Rres@0 net@14 a 2.424 +Rres@1 net@11 net@14 4.848 +Rres@2 b net@8 2.424 +Rres@3 net@8 net@11 4.848 +.ENDS wire-C_0_011f-419_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-419_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-419_5-R_34_667m +.ENDS wire90-419_5-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-276_8-R_34_667m a b +Ccap@0 gnd net@14 1.015f +Ccap@1 gnd net@8 1.015f +Ccap@2 gnd net@11 1.015f +Rres@0 net@14 a 1.599 +Rres@1 net@11 net@14 3.199 +Rres@2 b net@8 1.599 +Rres@3 net@8 net@11 3.199 +.ENDS wire-C_0_011f-276_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-276_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-276_8-R_34_667m +.ENDS wire90-276_8-layer_1-width_3 + *** CELL: stagesM:litDandP{sch} -.SUBCKT litDandP do[Lt] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] +.SUBCKT litDandP do[ins] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] +dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] +dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] +dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] @@ -4769,16 +4844,16 @@ Xnor2@0 ina inb out nor2_sy-X_10 +dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] +dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] +dsD[8] dsD[9] fire[M] flag[C] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] -+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] -+ps[8] ps[9] signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] -+sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] -XgaspLit@0 do[Lt] net@10 sir[9] net@99 net@27 gaspLit -Xinv@0 ps[17] net@77 inv-X_10 -Xlatch2in@0 take[A] net@81 dp[B] signalBitFromInboundSwitchFabric flag[C] ++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ++ps[7] ps[8] ps[9] signalBitFromInboundSwitchFabric succ[D] succ[T] +XbitAssig@0 bitAssignments +XgaspLit@1 do[ins] net@10 net@108 ps[27] gaspLit +Xinv@0 ps[17] net@112 inv-X_10 +Xlatch2in@0 take[A] net@83 dp[B] signalBitFromInboundSwitchFabric flag[C] +latch2in60C -XlatchAnd@1 ps[17] fire[M] take[A] latchAndDriver60 -XlatchAnd@2 net@77 fire[M] net@81 latchAndDriver30 -XlatchDri@0 net@13 take[B] latchDriver60 +XlatchAnd@3 net@111 fire[M] net@109 latchAndDriver30 +XlatchAnd@4 ps[17] fire[M] take[A] latchAndDriver60 +XlatchDri@1 net@13 take[B] latchDriver60 XnewDregi@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] +dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] +dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] @@ -4794,9 +4869,7 @@ XnewPathR@0 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] +dp[27] dp[28] dp[29] dp[30] dp[31] dp[32] dp[33] dp[34] fire[M] ps[10] ps[11] +ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] +ps[9] newPathReg -Xnor2n_sy@0 succ[T] succ[D] net@99 nor2n_sy-X_10 -XscanEx1@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1 +Xnor2n_sy@0 succ[T] succ[D] net@107 nor2n_sy-X_10 XsucANDdr@0 ps[16] fire[M] succ[D] sucANDdri60 XsucANDdr@1 ps[15] fire[M] succ[T] sucANDdri60 Xtc[1] tranCap @@ -4809,7 +4882,11 @@ Xtc[7] tranCap Xtc[8] tranCap Xtc[9] tranCap Xtc[10] tranCap -Xwire90@0 net@10 net@13 wire90-4175_4-layer_1-width_3 +Xtc[11] tranCap +Xwire90@0 net@10 net@13 wire90-632_9-layer_1-width_3 +Xwire90@1 net@108 net@107 wire90-402-layer_1-width_3 +Xwire90@2 net@109 net@83 wire90-419_5-layer_1-width_3 +Xwire90@3 net@112 net@111 wire90-276_8-layer_1-width_3 .ENDS litDandP *** CELL: redFive:pms2{sch} @@ -4854,20 +4931,84 @@ XPMOS@0 d g vdd PMOSx-X_10 .ENDS pms1-X_10 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-403-R_34_667m a b -Ccap@0 gnd net@14 1.478f -Ccap@1 gnd net@8 1.478f -Ccap@2 gnd net@11 1.478f -Rres@0 net@14 a 2.328 -Rres@1 net@11 net@14 4.657 -Rres@2 b net@8 2.328 -Rres@3 net@8 net@11 4.657 -.ENDS wire-C_0_011f-403-R_34_667m +.SUBCKT wire-C_0_011f-288_3-R_34_667m a b +Ccap@0 gnd net@14 1.057f +Ccap@1 gnd net@8 1.057f +Ccap@2 gnd net@11 1.057f +Rres@0 net@14 a 1.666 +Rres@1 net@11 net@14 3.331 +Rres@2 b net@8 1.666 +Rres@3 net@8 net@11 3.331 +.ENDS wire-C_0_011f-288_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-288_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-288_3-R_34_667m +.ENDS wire90-288_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-255_4-R_34_667m a b +Ccap@0 gnd net@14 0.936f +Ccap@1 gnd net@8 0.936f +Ccap@2 gnd net@11 0.936f +Rres@0 net@14 a 1.476 +Rres@1 net@11 net@14 2.951 +Rres@2 b net@8 1.476 +Rres@3 net@8 net@11 2.951 +.ENDS wire-C_0_011f-255_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-255_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-255_4-R_34_667m +.ENDS wire90-255_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-120_2-R_34_667m a b +Ccap@0 gnd net@14 0.441f +Ccap@1 gnd net@8 0.441f +Ccap@2 gnd net@11 0.441f +Rres@0 net@14 a 0.694 +Rres@1 net@11 net@14 1.389 +Rres@2 b net@8 0.694 +Rres@3 net@8 net@11 1.389 +.ENDS wire-C_0_011f-120_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-120_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-120_2-R_34_667m +.ENDS wire90-120_2-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-112_1-R_34_667m a b +Ccap@0 gnd net@14 0.411f +Ccap@1 gnd net@8 0.411f +Ccap@2 gnd net@11 0.411f +Rres@0 net@14 a 0.648 +Rres@1 net@11 net@14 1.295 +Rres@2 b net@8 0.648 +Rres@3 net@8 net@11 1.295 +.ENDS wire-C_0_011f-112_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-112_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-112_1-R_34_667m +.ENDS wire90-112_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-66_6-R_34_667m a b +Ccap@0 gnd net@14 0.244f +Ccap@1 gnd net@8 0.244f +Ccap@2 gnd net@11 0.244f +Rres@0 net@14 a 0.385 +Rres@1 net@11 net@14 0.77 +Rres@2 b net@8 0.385 +Rres@3 net@8 net@11 0.77 +.ENDS wire-C_0_011f-66_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-403-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-403-R_34_667m -.ENDS wire90-403-layer_1-width_3 +.SUBCKT wire90-66_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-66_6-R_34_667m +.ENDS wire90-66_6-layer_1-width_3 *** CELL: oneHotM:sucDri10Pair{sch} .SUBCKT sucDri10Pair bit[1] out[1][F] out[1][T] when @@ -4881,11 +5022,11 @@ Xnms1@2 net@139 net@154 nms1-X_4 Xnms2b@0 out[1][T] net@113 net@4 nms2-X_2 Xpms1@0 out[1][T] net@4 pms1-X_10 Xpms2_sy@0 out[1][F] net@105 bit[1] pms2_sy-X_10 -Xwire90@0 net@64 net@4 wire90-403-layer_1-width_3 -Xwire90@1 net@66 net@105 wire90-403-layer_1-width_3 -Xwire90@3 net@113 net@112 wire90-403-layer_1-width_3 -Xwire90@4 net@154 net@92 wire90-403-layer_1-width_3 -Xwire90@5 net@144 net@139 wire90-403-layer_1-width_3 +Xwire90@0 net@64 net@4 wire90-288_3-layer_1-width_3 +Xwire90@1 net@66 net@105 wire90-255_4-layer_1-width_3 +Xwire90@3 net@113 net@112 wire90-120_2-layer_1-width_3 +Xwire90@4 net@154 net@92 wire90-112_1-layer_1-width_3 +Xwire90@5 net@144 net@139 wire90-66_6-layer_1-width_3 .ENDS sucDri10Pair *** CELL: oneHotM:sucDri10Pairx6{sch} @@ -4901,6 +5042,102 @@ Xdd[6] bit[6] m1cate[6][F] m1cate[6][T] when sucDri10Pair Xnor2n_sy@0 m1cate[1][T] m1cate[1][F] ready nor2n_sy-X_5 .ENDS sucDri10Pairx6 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-425_8-R_34_667m a b +Ccap@0 gnd net@14 1.561f +Ccap@1 gnd net@8 1.561f +Ccap@2 gnd net@11 1.561f +Rres@0 net@14 a 2.46 +Rres@1 net@11 net@14 4.92 +Rres@2 b net@8 2.46 +Rres@3 net@8 net@11 4.92 +.ENDS wire-C_0_011f-425_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-425_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-425_8-R_34_667m +.ENDS wire90-425_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-257_3-R_34_667m a b +Ccap@0 gnd net@14 0.943f +Ccap@1 gnd net@8 0.943f +Ccap@2 gnd net@11 0.943f +Rres@0 net@14 a 1.487 +Rres@1 net@11 net@14 2.973 +Rres@2 b net@8 1.487 +Rres@3 net@8 net@11 2.973 +.ENDS wire-C_0_011f-257_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-257_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-257_3-R_34_667m +.ENDS wire90-257_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-692_7-R_34_667m a b +Ccap@0 gnd net@14 2.54f +Ccap@1 gnd net@8 2.54f +Ccap@2 gnd net@11 2.54f +Rres@0 net@14 a 4.002 +Rres@1 net@11 net@14 8.005 +Rres@2 b net@8 4.002 +Rres@3 net@8 net@11 8.005 +.ENDS wire-C_0_011f-692_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-692_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-692_7-R_34_667m +.ENDS wire90-692_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-399_3-R_34_667m a b +Ccap@0 gnd net@14 1.464f +Ccap@1 gnd net@8 1.464f +Ccap@2 gnd net@11 1.464f +Rres@0 net@14 a 2.307 +Rres@1 net@11 net@14 4.614 +Rres@2 b net@8 2.307 +Rres@3 net@8 net@11 4.614 +.ENDS wire-C_0_011f-399_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-399_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-399_3-R_34_667m +.ENDS wire90-399_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-489_2-R_34_667m a b +Ccap@0 gnd net@14 1.794f +Ccap@1 gnd net@8 1.794f +Ccap@2 gnd net@11 1.794f +Rres@0 net@14 a 2.826 +Rres@1 net@11 net@14 5.653 +Rres@2 b net@8 2.826 +Rres@3 net@8 net@11 5.653 +.ENDS wire-C_0_011f-489_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-489_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-489_2-R_34_667m +.ENDS wire90-489_2-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1763-R_34_667m a b +Ccap@0 gnd net@14 6.464f +Ccap@1 gnd net@8 6.464f +Ccap@2 gnd net@11 6.464f +Rres@0 net@14 a 10.186 +Rres@1 net@11 net@14 20.372 +Rres@2 b net@8 10.186 +Rres@3 net@8 net@11 20.372 +.ENDS wire-C_0_011f-1763-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1763-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1763-R_34_667m +.ENDS wire90-1763-layer_1-width_3 + *** CELL: oneHotM:minusOne{sch} .SUBCKT minusOne bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] fire[m1] headBit +m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] @@ -4918,14 +5155,30 @@ XsucDri10@1 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F] +m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] net@435 +net@421 sucDri10Pairx6 XsucDri20@1 net@407 succ[m1] sucDri20 -Xwire90@10 fire[m1] net@407 wire90-403-layer_1-width_3 -Xwire90@11 net@313 net@235 wire90-403-layer_1-width_3 -Xwire90@12 net@414 net@435 wire90-403-layer_1-width_3 -Xwire90@13 net@411 net@391 wire90-403-layer_1-width_3 -Xwire90@14 net@398 net@405 wire90-403-layer_1-width_3 -Xwire90@15 net@406 net@421 wire90-403-layer_1-width_3 +Xwire90@10 fire[m1] net@407 wire90-425_8-layer_1-width_3 +Xwire90@11 net@313 net@235 wire90-257_3-layer_1-width_3 +Xwire90@12 net@414 net@435 wire90-692_7-layer_1-width_3 +Xwire90@13 net@411 net@391 wire90-399_3-layer_1-width_3 +Xwire90@14 net@398 net@405 wire90-489_2-layer_1-width_3 +Xwire90@15 net@406 net@421 wire90-1763-layer_1-width_3 .ENDS minusOne +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-793_6-R_34_667m a b +Ccap@0 gnd net@14 2.91f +Ccap@1 gnd net@8 2.91f +Ccap@2 gnd net@11 2.91f +Rres@0 net@14 a 4.585 +Rres@1 net@11 net@14 9.17 +Rres@2 b net@8 4.585 +Rres@3 net@8 net@11 9.17 +.ENDS wire-C_0_011f-793_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-793_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-793_6-R_34_667m +.ENDS wire90-793_6-layer_1-width_3 + *** CELL: stagesM:mOneDockStage{sch} .SUBCKT mOneDockStage m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] +m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] @@ -4947,7 +5200,7 @@ Xins1in20@0 take[m1] ring[10] ring[11] ring[12] ring[13] ring[14] ring[15] +m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] +m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] +m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ins1in20Bx36 -XlatchDri@0 fire[1] take[m1] latchDriver60 +XlatchDri@1 fire[1] take[m1] latchDriver60 XminusOne@0 ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] net@11 +ring[30] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] +m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] @@ -4973,7 +5226,7 @@ Xtc[16] tranCap Xtc[17] tranCap Xtc[18] tranCap Xtc[19] tranCap -Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3 +Xwire90@1 net@11 fire[1] wire90-793_6-layer_1-width_3 .ENDS mOneDockStage *** CELL: loopCountM:mux10/2{sch} @@ -5021,29 +5274,63 @@ Xwire90@0 net@0 sT wire90-704_3-layer_1-width_3 Xwire90@1 net@1 sF wire90-704_3-layer_1-width_3 .ENDS muxForPS +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-4446_4-R_34_667m a b +Ccap@0 gnd net@14 16.303f +Ccap@1 gnd net@8 16.303f +Ccap@2 gnd net@11 16.303f +Rres@0 net@14 a 25.69 +Rres@1 net@11 net@14 51.381 +Rres@2 b net@8 25.69 +Rres@3 net@8 net@11 51.381 +.ENDS wire-C_0_011f-4446_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-4446_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-4446_4-R_34_667m +.ENDS wire90-4446_4-layer_1-width_3 + *** CELL: registersM:dockPSreg{sch} -.SUBCKT dockPSreg fire[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] +.SUBCKT dockPSreg do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] +m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] -+m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] -+m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] outLO[1] outLO[2] outLO[3] outLO[4] -+outLO[5] outLO[6] outLO[7] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] -+ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] -+ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] -+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[1] -Xins1in20@0 take[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] -+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] -+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] -+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] -+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] -+ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] -+ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ins1in20Bx36 -XlatchDri@0 fire[1] net@0 latchDriver60 ++m1[27] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] outLO[1] outLO[2] ++outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[10] ps[11] ps[12] ps[13] ++ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ++ps[24] ps[25] ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] +Xinv@0 do[ins] net@1 inv-X_40 +Xlx[1] hold[1] m1[1] ps[1] latch1in20B +Xlx[2] hold[1] m1[2] ps[2] latch1in20B +Xlx[3] hold[1] m1[3] ps[3] latch1in20B +Xlx[4] hold[1] m1[4] ps[4] latch1in20B +Xlx[5] hold[1] m1[5] ps[5] latch1in20B +Xlx[6] hold[1] m1[6] ps[6] latch1in20B +Xlx[7] hold[1] m1[7] ps[7] latch1in20B +Xlx[8] hold[1] m1[8] ps[8] latch1in20B +Xlx[9] hold[1] m1[9] ps[9] latch1in20B +Xlx[10] hold[1] m1[10] ps[10] latch1in20B +Xlx[11] hold[1] m1[11] ps[11] latch1in20B +Xlx[12] hold[1] m1[12] ps[12] latch1in20B +Xlx[13] hold[1] m1[13] ps[13] latch1in20B +Xlx[14] hold[1] m1[14] ps[14] latch1in20B +Xlx[15] hold[1] m1[15] ps[15] latch1in20B +Xlx[16] hold[1] m1[16] ps[16] latch1in20B +Xlx[17] hold[1] m1[17] ps[17] latch1in20B +Xlx[18] hold[1] m1[18] ps[18] latch1in20B +Xlx[19] hold[1] m1[19] ps[19] latch1in20B +Xlx[20] hold[1] m1[20] ps[20] latch1in20B +Xlx[21] hold[1] m1[21] ps[21] latch1in20B +Xlx[22] hold[1] m1[22] ps[22] latch1in20B +Xlx[23] hold[1] m1[23] ps[23] latch1in20B +Xlx[24] hold[1] m1[24] ps[24] latch1in20B +Xlx[25] hold[1] m1[25] ps[25] latch1in20B +Xlx[26] hold[1] m1[26] ps[26] latch1in20B +Xlx[27] hold[1] m1[27] ps[27] latch1in20B XmuxForOD@0 ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[8] outLO[1] outLO[2] +outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForPS Xtc[1] tranCap Xtc[2] tranCap Xtc[3] tranCap -Xwire90@0 net@0 take[1] wire90-544_2-layer_1-width_3 +Xwire90@0 net@1 hold[1] wire90-4446_4-layer_1-width_3 .ENDS dockPSreg *** CELL: redFive:nand2n{sch} @@ -6048,19 +6335,6 @@ Xwire90@42 net@423 bitt[7] wire90-1291_5-layer_1-width_3 Xwire90@43 net@426 do[7] wire90-1019_7-layer_1-width_3 .ENDS ilc -*** CELL: driversL:predORdri20wMC{sch} -.SUBCKT predORdri20wMC inA inB mc pred -XNMOSx@0 pred inA gnd NMOSx-X_20 -XNMOSx@1 pred mc gnd NMOSx-X_4 -XNMOSx@2 pred inB gnd NMOSx-X_20 -XPMOSx@1 pred net@217 net@203 PMOSx-X_4 -XPMOSx@2 net@203 inB net@204 PMOSx-X_4 -XPMOSx@3 net@204 inA net@205 PMOSx-X_4 -XPMOSx@4 net@205 mc vdd PMOSx-X_4 -Xinv@0 pred net@145 inv-X_4 -Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3 -.ENDS predORdri20wMC - *** CELL: redFive:nand2n{sch} .SUBCKT nand2n-X_20 ina inb out Xnand2@0 ina inb out nand2-X_20 @@ -6228,22 +6502,6 @@ Xwire@0 a b wire-C_0_011f-392_9-R_34_667m .ENDS wire90-392_9-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-174_7-R_34_667m a b -Ccap@0 gnd net@14 0.641f -Ccap@1 gnd net@8 0.641f -Ccap@2 gnd net@11 0.641f -Rres@0 net@14 a 1.009 -Rres@1 net@11 net@14 2.019 -Rres@2 b net@8 1.009 -Rres@3 net@8 net@11 2.019 -.ENDS wire-C_0_011f-174_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-174_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-174_7-R_34_667m -.ENDS wire90-174_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-1154_9-R_34_667m a b Ccap@0 gnd net@14 4.235f Ccap@1 gnd net@8 4.235f @@ -6275,41 +6533,55 @@ Rres@3 net@8 net@11 6.824 Xwire@0 a b wire-C_0_011f-590_5-R_34_667m .ENDS wire90-590_5-layer_1-width_3 -*** CELL: moveM:races{sch} -.SUBCKT races bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] in[D] in[T] succ torp -+winLO[M] +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-174_7-R_34_667m a b +Ccap@0 gnd net@14 0.641f +Ccap@1 gnd net@8 0.641f +Ccap@2 gnd net@11 0.641f +Rres@0 net@14 a 1.009 +Rres@1 net@11 net@14 2.019 +Rres@2 b net@8 1.009 +Rres@3 net@8 net@11 2.019 +.ENDS wire-C_0_011f-174_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-174_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-174_7-R_34_667m +.ENDS wire90-174_7-layer_1-width_3 + +*** CELL: moveM:moveRepeat{sch} +.SUBCKT moveRepeat do[ins] fire[T] in[D] in[T] sel[Di] sel[Mv] sel[Ti] ++sel[Tp] succ[sf] torp winLO[M] Xarbiter2@0 net@131 net@128 torp in[D] arbiter2 Xarbiter2@1 net@130 net@129 torp in[T] arbiter2 -Xinv@0 winLO[M] net@192 inv-X_5 XinvI@0 net@150 fire[T] inv-X_20 -XinvI@1 net@187 net@186 inv-X_5 -XinvI@3 net@187 invI@3_out inv-X_10 -Xnand2@0 bit[Di] do[Tp] net@35 nand2-X_10 -Xnand2@1 bit[Ti] do[Tp] net@42 nand2-X_10 -Xnand2@2 net@94 do[Mv] net@86 nand2-X_10 -Xnand2n@0 bit[Di] net@11 net@57 nand2n-X_20 -Xnand2n@1 bit[Ti] net@53 net@60 nand2n-X_20 -Xnand3in4@0 net@159 net@123 net@98 winLO[M] nand3in44s -Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_20 -Xnor2n@0 net@39 net@12 net@44 nor2n-X_20 -Xnor2n@1 net@36 net@32 net@43 nor2n-X_20 -Xnor2n@2 succ net@153 net@152 nor2n-X_20 +XinvI@6 net@271 net@217 inv-X_5 +XinvI@7 net@224 invI@7_out inv-X_10 +Xnand2@2 net@224 do[ins] net@86 nand2-X_10 +Xnand2@5 winLO[M] sel[Mv] net@221 nand2-X_5 +Xnand2@6 sel[Tp] do[ins] net@254 nand2-X_10 +Xnand2n@0 sel[Di] net@11 net@57 nand2n-X_20 +Xnand2n@1 sel[Ti] net@53 net@60 nand2n-X_20 +Xnand3in4@0 net@159 net@127 net@98 winLO[M] nand3in44s +Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_10 +Xnor2n@0 net@38 net@12 net@44 nor2n-X_10 +Xnor2n@1 net@38 net@32 net@43 nor2n-X_10 +Xnor2n@2 succ[sf] net@153 net@152 nor2n-X_20 Xwire90@0 net@131 net@12 wire90-321_9-layer_1-width_3 Xwire90@1 net@130 net@32 wire90-321_9-layer_1-width_3 Xwire90@2 net@129 net@53 wire90-294-layer_1-width_3 Xwire90@3 net@128 net@11 wire90-294-layer_1-width_3 -Xwire90@4 net@35 net@39 wire90-572_3-layer_1-width_3 -Xwire90@5 net@42 net@36 wire90-572_3-layer_1-width_3 +Xwire90@4 net@254 net@38 wire90-572_3-layer_1-width_3 Xwire90@6 net@44 net@45 wire90-741_5-layer_1-width_3 Xwire90@7 net@43 net@48 wire90-783-layer_1-width_3 -Xwire90@8 net@60 net@123 wire90-1254_1-layer_1-width_3 +Xwire90@8 net@60 net@127 wire90-1254_1-layer_1-width_3 Xwire90@9 net@57 net@159 wire90-1300_1-layer_1-width_3 Xwire90@11 net@86 net@153 wire90-392_9-layer_1-width_3 -Xwire90@12 net@94 net@186 wire90-174_7-layer_1-width_3 Xwire90@13 net@152 net@98 wire90-1154_9-layer_1-width_3 Xwire90@15 net@151 net@150 wire90-590_5-layer_1-width_3 -Xwire90@16 net@187 net@192 wire90-174_7-layer_1-width_3 -.ENDS races +Xwire90@19 net@224 net@217 wire90-174_7-layer_1-width_3 +Xwire90@20 net@271 net@221 wire90-174_7-layer_1-width_3 +.ENDS moveRepeat *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-362_9-R_34_667m a b @@ -6376,44 +6648,47 @@ Xwire@0 a b wire-C_0_011f-709_6-R_34_667m .ENDS wire90-709_6-layer_1-width_3 *** CELL: moveM:moveOut{sch} -.SUBCKT moveOut bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] -+flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5] +.SUBCKT moveOut do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[do] ++ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] sel[Di] sel[Mv] sel[Ti] sel[Tp] +succ[sf] winLO[M] -Xinv@0 net@28 s[4] inv-X_10 -Xinv@1 net@29 s[3] inv-X_10 -Xinv@2 net@50 s[5] inv-X_10 -Xinv@9 fire[T] net@186 inv-X_5 -Xinv@10 ilc[do] net@221 inv-X_5 -Xinv@11 net@227 s[2] inv-X_10 -Xinv@12 net@194 s[1] inv-X_10 -XinvI@0 do[Tp] net@28 inv-X_5 -XinvI@1 epi[torp] net@29 inv-X_5 -XinvI@2 do[Mv] net@50 inv-X_5 -XinvI@7 pred[D] net@227 inv-X_5 -XinvI@8 pred[T] net@194 inv-X_5 -Xnand2@2 ilc[do] bit[Di] net@208 nand2-X_5 -Xnand2@3 ilc[do] bit[Ti] net@207 nand2-X_5 +Xinv@9 fire[T] net@326 inv-X_5 +Xinv@10 ilc[do] net@221 inv-X_10 +Xinv@13 pred[T] net@194 inv-X_5 +Xinv@14 pred[D] net@227 inv-X_5 +Xinv@15 epi[torp] net@29 inv-X_5 +Xinv@16 net@250 doneLO[M] inv-X_20 +XinvI@9 net@194 s[1] inv-X_10 +XinvI@10 net@227 s[2] inv-X_10 +XinvI@11 net@29 s[3] inv-X_10 +XmoveRepe@0 do[ins] fire[T] pred[D] pred[T] sel[Di] sel[Mv] sel[Ti] sel[Tp] ++succ[sf] epi[torp] winLO[M] moveRepeat +Xnand2@2 ilc[do] sel[Di] net@208 nand2-X_5 +Xnand2@3 ilc[do] sel[Ti] net@207 nand2-X_5 Xnor2n@1 ilc[mo] winLO[M] net@250 nor2n-X_10 Xnor2n@5 net@206 winLO[M] net@203 nor2n-X_10 Xnor2n@6 net@205 winLO[M] net@204 nor2n-X_10 Xnor2n@7 net@220 winLO[M] fire[M] nor2n-X_20 -Xpms1@0 flag[D][set] net@186 pms1-X_20 +Xpms1@0 flag[D][set] net@327 pms1-X_20 XpredDri2@0 fire[T] mc epi[torp] predDri20wMC XpredDri2@3 net@201 mc pred[D] predDri20wMC XpredDri2@4 net@200 mc pred[T] predDri20wMC -XpredORdr@0 fire[T] done[M] mc do[Tp] predORdri20wMC -XpredORdr@1 fire[T] done[M] mc do[Mv] predORdri20wMC -Xraces@0 bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] pred[D] pred[T] succ[sf] -+epi[torp] winLO[M] races -XsucDri20@0 done[M] do[reD] sucDri20 +XpredDri4@0 net@345 do[ins] predDri40 +XpredDri4@1 net@340 do[ins] predDri40 Xwire90@9 net@206 net@208 wire90-362_9-layer_1-width_3 Xwire90@10 net@220 net@221 wire90-602_7-layer_1-width_3 Xwire90@11 net@200 net@204 wire90-269_9-layer_1-width_3 Xwire90@12 net@201 net@203 wire90-269_9-layer_1-width_3 Xwire90@13 net@205 net@207 wire90-362_9-layer_1-width_3 -Xwire90@15 done[M] net@250 wire90-709_6-layer_1-width_3 +Xwire90@15 net@345 net@250 wire90-709_6-layer_1-width_3 +Xwire90@16 net@340 fire[T] wire90-269_9-layer_1-width_3 +Xwire90@17 net@326 net@327 wire90-269_9-layer_1-width_3 .ENDS moveOut +*** CELL: scanM:scanEx1h{sch} +.SUBCKT scanEx1h dIn[1] mc p1p p2p rd sin sout +XscanCell@10 dIn[1] p1p p2p rd sin sout scanCellE +.ENDS scanEx1h + *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-297_9-R_34_667m a b Ccap@0 gnd net@14 1.092f @@ -6625,19 +6900,19 @@ Xwire@0 a b wire-C_0_011f-1831_6-R_34_667m .ENDS wire90-1831_6-layer_1-width_3 *** CELL: moveM:ilcMoveOut{sch} -.SUBCKT ilcMoveOut bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] -+flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] -+inLO[8] mc p1p p2p pred[D] pred[T] rd sin sout succ[sf] +.SUBCKT ilcMoveOut do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[load] ++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] mc p1p p2p pred[D] ++pred[T] rd sel[Di] sel[Mv] sel[Ti] sel[Tp] sin sout succ[sf] Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8] +ilc[decLO] ilc[do] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] +inLO[6] inLO[8] ilc -XoutDockM@0 bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] -+flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5] -+succ[sf] net@72 moveOut -XscanEx2h@0 s[1] s[5] mc p1p p2p rd net@51 net@58 scanEx2h -XscanEx3h@0 s[4] s[3] s[2] mc p1p p2p rd net@58 sout scanEx3h +XoutDockM@0 do[ins] doneLO[M] epi[torp] fire[M] flag[D][set] ilc[do] ilc[mo] ++mc pred[D] pred[T] s[1] s[2] s[3] sel[Di] sel[Mv] sel[Ti] sel[Tp] succ[sf] ++net@72 moveOut +XscanEx1h@0 s[3] mc p1p p2p rd net@84 sout scanEx1h +XscanEx2h@0 s[1] s[2] mc p1p p2p rd net@85 net@84 scanEx2h XscanEx4h@0 bitt[1] bitt[3] bitt[5] bitt[7] mc p1p p2p rd sin net@50 scanEx4h -XscanEx4h@1 bitt[2] bitt[4] bitt[6] bitt[8] mc p1p p2p rd net@50 net@51 +XscanEx4h@1 bitt[2] bitt[4] bitt[6] bitt[8] mc p1p p2p rd net@50 net@85 +scanEx4h Xwire90@0 net@72 ilc[decLO] wire90-4243_4-layer_1-width_3 Xwire90@1 wire90@1_a ilc[mo] wire90-467_9-layer_1-width_3 @@ -6663,10 +6938,6 @@ Xwire90@0 net@0 sF wire90-704_3-layer_1-width_3 Xwire90@1 net@1 sT wire90-704_3-layer_1-width_3 .ENDS muxForD -*** CELL: wiresL:bitAssignments{sch} -.SUBCKT bitAssignments -.ENDS bitAssignments - *** CELL: redFive:nand2_sy{sch} .SUBCKT nand2_sy-X_30 ina inb out XPMOS@0 out inb vdd PMOSx-X_30 @@ -6700,70 +6971,6 @@ Xpms1@2 out inA pms1-X_3 Xpms1@3 out resetLO pms1-X_20 .ENDS nand3in20sr -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_5_5 d g s -MNMOSf@0 d g s gnd nch W='16.5*(1+ABN/sqrt(16.5*2))' L='2' -+DELVTO='AVT0N/sqrt(16.5*2)' -.ENDS NMOSx-X_5_5 - -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_5_5 d g s -MPMOSf@0 d g s vdd pch W='33*(1+ABP/sqrt(33*2))' L='2' -+DELVTO='AVT0P/sqrt(33*2)' -.ENDS PMOSx-X_5_5 - -*** CELL: redFive:pms2{sch} -.SUBCKT pms2-X_2_75 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_5_5 -XPMOS@1 d g2 net@2 PMOSx-X_5_5 -.ENDS pms2-X_2_75 - -*** CELL: redFive:pms2_sy{sch} -.SUBCKT pms2_sy-X_5_5 d g g2 -Xpms2@0 d g g2 pms2-X_2_75 -Xpms2@1 d g2 g pms2-X_2_75 -.ENDS pms2_sy-X_5_5 - -*** CELL: redFive:nor2_sy{sch} -.SUBCKT nor2_sy-X_5_5 ina inb out -XNMOS@0 out inb gnd NMOSx-X_5_5 -XNMOS@1 out ina gnd NMOSx-X_5_5 -Xpms2_sy@0 out ina inb pms2_sy-X_5_5 -.ENDS nor2_sy-X_5_5 - -*** CELL: redFive:nor2n_sy{sch} -.SUBCKT nor2n_sy-X_5_5 ina inb out -Xnor2@0 ina inb out nor2_sy-X_5_5 -.ENDS nor2n_sy-X_5_5 - -*** CELL: driversL:sucDri20plain{sch} -.SUBCKT sucDri20plain in succ -XPMOSx@0 succ in vdd PMOSx-X_20 -Xinv@1 succ net@94 inv-X_4 -Xnms2@0 succ net@127 in nms2-X_2 -Xwire90@0 net@127 net@94 wire90-124_7-layer_1-width_3 -.ENDS sucDri20plain - -*** CELL: predicateM:predSucDri{sch} -.SUBCKT predSucDri do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co] -+sel[Ld] sel[Lt] sel[Mv] sel[Tp] -Xna[1] sel[Ld] fire[do] w[1] nand2-X_10 -Xna[2] sel[Co] fire[do] w[2] nand2-X_10 -Xna[3] sel[Mv] fire[do] w[3] nand2-X_10 -Xna[4] sel[Tp] fire[do] w[4] nand2-X_10 -Xna[5] sel[Lt] fire[do] w[5] nand2-X_10 -Xsd[1] w[1] do[Ld] sucDri20plain -Xsd[2] w[2] do[Co] sucDri20plain -Xsd[3] w[3] do[Mv] sucDri20plain -Xsd[4] w[4] do[Tp] sucDri20plain -Xsd[5] w[5] do[Lt] sucDri20plain -Xwire90@0 w[1] wire90@0_b wire90-503_4-layer_1-width_3 -Xwire90@1 w[2] wire90@1_b wire90-503_4-layer_1-width_3 -Xwire90@2 w[3] wire90@2_b wire90-503_4-layer_1-width_3 -Xwire90@3 w[4] wire90@3_b wire90-503_4-layer_1-width_3 -Xwire90@4 w[5] wire90@4_b wire90-503_4-layer_1-width_3 -.ENDS predSucDri - *** CELL: redFive:pms2{sch} .SUBCKT pms2-X_1_5 d g g2 XPMOS@0 net@2 g vdd PMOSx-X_3 @@ -6802,7 +7009,7 @@ Rres@3 net@8 net@11 0.696 Xwire@0 a b wire-C_0_011f-60_2-R_34_667m .ENDS wire90-60_2-layer_1-width_3 -*** CELL: driversL:predCond20wMC{sch} +*** CELL: driversM:predCond20wMC{sch} .SUBCKT predCond20wMC cond in mc pred XNMOSx@1 pred mc gnd NMOSx-X_10 XPMOSx@0 pred in net@217 PMOSx-X_3 @@ -6830,7 +7037,7 @@ Rres@3 net@8 net@11 2.536 Xwire@0 a b wire-C_0_011f-219_5-R_34_667m .ENDS wire90-219_5-layer_1-width_3 -*** CELL: driversL:predCond20wMS{sch} +*** CELL: driversM:predCond20wMS{sch} .SUBCKT predCond20wMS cond in mc pred XPMOSx@0 pred cond net@210 PMOSx-X_3 XPMOSx@1 pred in net@217 PMOSx-X_3 @@ -6855,19 +7062,47 @@ XpredCond@0 sel[rD] fire[do] mc flag[D][clr] predCond20wMC XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS .ENDS predFlagDri +*** CELL: redFive:nms1{sch} +.SUBCKT nms1-X_10 d g +XNMOS@1 d g gnd NMOSx-X_10 +.ENDS nms1-X_10 + +*** CELL: redFive:pms1{sch} +.SUBCKT pms1-X_4 d g +XPMOS@0 d g vdd PMOSx-X_4 +.ENDS pms1-X_4 + +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_40 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_80 +XPMOS@1 d g2 net@2 PMOSx-X_80 +.ENDS pms2-X_40 + +*** CELL: driversM:sucNANDdri40keep{sch} +.SUBCKT sucNANDdri40keep in inB mc succ +MNMOS4fwk@0 gnd net@164 succ NMOS4fwk@0_b nch W='3*(1+ABN/sqrt(3*2))' L='2' ++DELVTO='AVT0N/sqrt(3*2)' +MPMOS4fwk@1 net@174 net@164 succ PMOS4fwk@1_b pch W='3*(1+ABP/sqrt(3*2))' ++L='2' DELVTO='AVT0P/sqrt(3*2)' +Xinv@3 succ net@167 inv-X_4 +XinvI@0 in net@144 inv-X_20 +Xnms1@0 succ mc nms1-X_10 +Xpms1@0 net@174 mc pms1-X_4 +Xpms2a@0 succ inB net@145 pms2-X_40 +Xwire90@1 net@144 net@145 wire90-503_4-layer_1-width_3 +Xwire90@2 net@167 net@164 wire90-124_7-layer_1-width_3 +.ENDS sucNANDdri40keep + *** CELL: predicateM:ohPredDo{sch} -.SUBCKT ohPredDo do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] fire[skip] -+flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] -+mc ps[do] ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] +.SUBCKT ohPredDo do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set] ++flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[do] ++ps[skip] XbitAssig@0 bitAssignments -Xinv@1 fire[do] net@125 inv-X_20 -Xinv@2 net@125 net@57 inv-X_20 -XohPredDo@3 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] net@57 sel[Co] sel[Ld] sel[Lt] -+sel[Mv] sel[Tp] predSucDri -XpredFlag@1 net@57 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] -+flag[D][clr] flag[D][set] mc sel[Fl] sel[rD] predFlagDri +XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] ++flag[D][clr] flag[D][set] mc m1[Fl] m1[rD] predFlagDri XsucDri20@0 net@55 ps[skip] sucDri20 -XsucDri20@1 net@57 ps[do] sucDri20 +XsucDri20@1 fire[do] ps[do] sucDri20 +XsucNANDd@0 fire[do] m1[Fl] mc do[ins] sucNANDdri40keep Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3 .ENDS ohPredDo @@ -7218,136 +7453,386 @@ Rres@3 net@8 net@11 29.083 Xwire@0 a b wire-C_0_011f-2516_8-R_34_667m .ENDS wire90-2516_8-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-247_4-R_34_667m a b -Ccap@0 gnd net@14 0.907f -Ccap@1 gnd net@8 0.907f -Ccap@2 gnd net@11 0.907f -Rres@0 net@14 a 1.429 -Rres@1 net@11 net@14 2.859 -Rres@2 b net@8 1.429 -Rres@3 net@8 net@11 2.859 -.ENDS wire-C_0_011f-247_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-247_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-247_4-R_34_667m -.ENDS wire90-247_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-249_4-R_34_667m a b -Ccap@0 gnd net@14 0.914f -Ccap@1 gnd net@8 0.914f -Ccap@2 gnd net@11 0.914f -Rres@0 net@14 a 1.441 -Rres@1 net@11 net@14 2.882 -Rres@2 b net@8 1.441 -Rres@3 net@8 net@11 2.882 -.ENDS wire-C_0_011f-249_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-249_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-249_4-R_34_667m -.ENDS wire90-249_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-244_3-R_34_667m a b -Ccap@0 gnd net@14 0.896f -Ccap@1 gnd net@8 0.896f -Ccap@2 gnd net@11 0.896f -Rres@0 net@14 a 1.412 -Rres@1 net@11 net@14 2.823 -Rres@2 b net@8 1.412 -Rres@3 net@8 net@11 2.823 -.ENDS wire-C_0_011f-244_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-244_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-244_3-R_34_667m -.ENDS wire90-244_3-layer_1-width_3 - *** CELL: predicateM:ohPredAll{sch} -.SUBCKT ohPredAll do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr] -+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] -+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] -+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p -+ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] -+sin sout +.SUBCKT ohPredAll do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] ++flag[D][clr] flag[D][set] m1[Fl] m1[rD] m1cate[1][F] m1cate[1][T] ++m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] ++m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p ps[do] ++ps[skip] rd sin sout XbitAssig@0 bitAssignments -XinvI@0 net@82 fire[do] inv-X_40 -XinvI@1 net@63 fire[skip] inv-X_10 -XinvI@2 net@183 net@186 inv-X_10 +Xinv@1 do[ins] net@206 inv-X_5 +XinvI@0 net@82 net@166 inv-X_40 +XinvI@1 net@63 net@144 inv-X_10 +XinvI@2 do[ins] net@193 inv-X_10 +XinvI@3 net@200 s[3] inv-X_10 Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10 -Xnand2_sy@1 net@177 net@174 net@182 nand2_sy-X_6 Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30 Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_10 -Xnor2n_sy@2 do[Mv] do[Lt] net@173 nor2n_sy-X_5_5 -Xnor2n_sy@3 do[Ld] do[Co] net@180 nor2n_sy-X_5_5 -XohPredDo@1 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] net@149 flag[A][clr] -+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] mc ps[do] -+ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] ohPredDo +XohPredDo@1 do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set] ++flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[do] ++ps[skip] ohPredDo XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr] +flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] +m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] +m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred -XscanEx2h@0 s[1] s[2] mc p1p p2p rd sin sout scanEx2h +XscanEx3h@0 s[1] s[2] s[3] mc p1p p2p rd sin sout scanEx3h Xwire90@0 net@39 net@11 wire90-1000_9-layer_1-width_3 -Xwire90@1 net@186 net@41 wire90-544-layer_1-width_3 +Xwire90@1 net@193 net@41 wire90-544-layer_1-width_3 Xwire90@2 net@46 net@139 wire90-863_3-layer_1-width_3 Xwire90@3 net@21 net@19 wire90-355_3-layer_1-width_3 Xwire90@4 net@82 net@84 wire90-1035_5-layer_1-width_3 Xwire90@5 net@147 net@63 wire90-602_8-layer_1-width_3 Xwire90@6 net@92 net@94 wire90-613_9-layer_1-width_3 -Xwire90@7 net@149 fire[skip] wire90-782-layer_1-width_3 +Xwire90@7 fire[skip] net@144 wire90-782-layer_1-width_3 Xwire90@9 fire[both] net@160 wire90-2516_8-layer_1-width_3 -Xwire90@10 net@173 net@174 wire90-247_4-layer_1-width_3 -Xwire90@11 net@180 net@177 wire90-249_4-layer_1-width_3 -Xwire90@12 net@182 net@183 wire90-244_3-layer_1-width_3 +Xwire90@10 net@206 net@200 wire90-215_4-layer_1-width_3 +Xwire90@11 net@166 fire[do] wire90-782-layer_1-width_3 .ENDS ohPredAll +*** CELL: centersJ:ctrAND2in100{sch} +.SUBCKT ctrAND2in100 inA inB out +Xinv@9 net@163 net@161 inv-X_30 +XinvI@1 net@162 out inv-X_100 +Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10 +Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3 +Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3 +.ENDS ctrAND2in100 + *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b -Ccap@0 gnd net@14 6.469f -Ccap@1 gnd net@8 6.469f -Ccap@2 gnd net@11 6.469f -Rres@0 net@14 a 10.194 -Rres@1 net@11 net@14 20.389 -Rres@2 b net@8 10.194 -Rres@3 net@8 net@11 20.389 -.ENDS wire-C_0_011f-1764_4-R_34_667m +.SUBCKT wire-C_0_011f-431_3-R_34_667m a b +Ccap@0 gnd net@14 1.581f +Ccap@1 gnd net@8 1.581f +Ccap@2 gnd net@11 1.581f +Rres@0 net@14 a 2.492 +Rres@1 net@11 net@14 4.984 +Rres@2 b net@8 2.492 +Rres@3 net@8 net@11 4.984 +.ENDS wire-C_0_011f-431_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1764_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m -.ENDS wire90-1764_4-layer_1-width_3 +.SUBCKT wire90-431_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-431_3-R_34_667m +.ENDS wire90-431_3-layer_1-width_3 + +*** CELL: loopCountM:ilcLoad{sch} +.SUBCKT ilcLoad do[ins] ilc[load] sel[Ld] sel[rD] +XctrAND2i@0 sel[rD] net@12 ilc[load] ctrAND2in100 +Xnand2@0 sel[Ld] do[ins] net@23 nand2-X_5 +XpredDri4@0 ilc[load] do[ins] predDri40 +Xwire90@0 net@23 net@12 wire90-431_3-layer_1-width_3 +.ENDS ilcLoad + +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_3_999 d g s +MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2' ++DELVTO='AVT0N/sqrt(11.997*2)' +.ENDS NMOSx-X_3_999 + +*** CELL: redFive:nms3{sch} +.SUBCKT nms3-X_1_333 d g g2 g3 +XNMOS@0 d g3 net@6 NMOSx-X_3_999 +XNMOS@1 net@7 g gnd NMOSx-X_3_999 +XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999 +.ENDS nms3-X_1_333 + +*** CELL: driversM:sucDri20or{sch} +.SUBCKT sucDri20or inA inB succ +Xinv@1 succ net@94 inv-X_4 +Xnms3b@0 succ net@142 inB inA nms3-X_1_333 +Xpms1@0 succ inA pms1-X_20 +Xpms1@1 succ inB pms1-X_20 +Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3 +.ENDS sucDri20or *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b -Ccap@0 gnd net@14 5.036f -Ccap@1 gnd net@8 5.036f -Ccap@2 gnd net@11 5.036f -Rres@0 net@14 a 7.935 -Rres@1 net@11 net@14 15.87 -Rres@2 b net@8 7.935 -Rres@3 net@8 net@11 15.87 -.ENDS wire-C_0_011f-1373_4-R_34_667m +.SUBCKT wire-C_0_011f-406_2-R_34_667m a b +Ccap@0 gnd net@14 1.489f +Ccap@1 gnd net@8 1.489f +Ccap@2 gnd net@11 1.489f +Rres@0 net@14 a 2.347 +Rres@1 net@11 net@14 4.694 +Rres@2 b net@8 2.347 +Rres@3 net@8 net@11 4.694 +.ENDS wire-C_0_011f-406_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1373_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m -.ENDS wire90-1373_4-layer_1-width_3 +.SUBCKT wire90-406_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-406_2-R_34_667m +.ENDS wire90-406_2-layer_1-width_3 -*** CELL: loopCountM:olcEven{sch} -.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2] -+inLO[4] inLO[6] load[T] -Xinv@2 count[T] net@210 inv-X_30 -Xinv@3 load[T] net@211 inv-X_30 -XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB -XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB -XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB -Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3 -Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-488_9-R_34_667m a b +Ccap@0 gnd net@14 1.793f +Ccap@1 gnd net@8 1.793f +Ccap@2 gnd net@11 1.793f +Rres@0 net@14 a 2.825 +Rres@1 net@11 net@14 5.65 +Rres@2 b net@8 2.825 +Rres@3 net@8 net@11 5.65 +.ENDS wire-C_0_011f-488_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-488_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-488_9-R_34_667m +.ENDS wire90-488_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-348_7-R_34_667m a b +Ccap@0 gnd net@14 1.279f +Ccap@1 gnd net@8 1.279f +Ccap@2 gnd net@11 1.279f +Rres@0 net@14 a 2.015 +Rres@1 net@11 net@14 4.029 +Rres@2 b net@8 2.015 +Rres@3 net@8 net@11 4.029 +.ENDS wire-C_0_011f-348_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-348_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-348_7-R_34_667m +.ENDS wire90-348_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-411_6-R_34_667m a b +Ccap@0 gnd net@14 1.509f +Ccap@1 gnd net@8 1.509f +Ccap@2 gnd net@11 1.509f +Rres@0 net@14 a 2.378 +Rres@1 net@11 net@14 4.756 +Rres@2 b net@8 2.378 +Rres@3 net@8 net@11 4.756 +.ENDS wire-C_0_011f-411_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-411_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-411_6-R_34_667m +.ENDS wire90-411_6-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-147_3-R_34_667m a b +Ccap@0 gnd net@14 0.54f +Ccap@1 gnd net@8 0.54f +Ccap@2 gnd net@11 0.54f +Rres@0 net@14 a 0.851 +Rres@1 net@11 net@14 1.702 +Rres@2 b net@8 0.851 +Rres@3 net@8 net@11 1.702 +.ENDS wire-C_0_011f-147_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-147_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-147_3-R_34_667m +.ENDS wire90-147_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-143_2-R_34_667m a b +Ccap@0 gnd net@14 0.525f +Ccap@1 gnd net@8 0.525f +Ccap@2 gnd net@11 0.525f +Rres@0 net@14 a 0.827 +Rres@1 net@11 net@14 1.655 +Rres@2 b net@8 0.827 +Rres@3 net@8 net@11 1.655 +.ENDS wire-C_0_011f-143_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-143_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-143_2-R_34_667m +.ENDS wire90-143_2-layer_1-width_3 + +*** CELL: loopCountM:olcControlD{sch} +.SUBCKT olcControlD fire[Co] fire[zz] flag[D][clr] flag[D][set] olc[zero] ++olc[zoo] s[1] s[2] +Xinv@6 olc[zoo] net@180 inv-X_5 +Xinv@7 olc[zero] net@184 inv-X_5 +Xinv@18 flag[D][set] net@550 inv-X_5 +Xinv@19 flag[D][clr] net@545 inv-X_5 +XinvI@0 net@544 s[2] inv-X_10 +XinvI@1 net@549 s[1] inv-X_10 +Xnand2@0 net@288 fire[Co] net@286 nand2-X_5 +Xnand2@1 net@289 fire[zz] net@284 nand2-X_5 +Xnand2@2 olc[zoo] fire[Co] net@279 nand2-X_5 +Xnand2@3 olc[zero] fire[zz] net@281 nand2-X_5 +XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or +XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or +Xwire90@9 net@281 net@422 wire90-406_2-layer_1-width_3 +Xwire90@10 net@279 net@426 wire90-488_9-layer_1-width_3 +Xwire90@11 net@286 net@428 wire90-348_7-layer_1-width_3 +Xwire90@12 net@284 net@424 wire90-411_6-layer_1-width_3 +Xwire90@13 net@180 net@288 wire90-147_3-layer_1-width_3 +Xwire90@14 net@184 net@289 wire90-143_2-layer_1-width_3 +Xwire90@21 net@550 net@549 wire90-142_6-layer_1-width_3 +Xwire90@22 net@545 net@544 wire90-142_6-layer_1-width_3 +.ENDS olcControlD + +*** CELL: loopCountM:olcCount{sch} +.SUBCKT olcCount do[ins] fire[Co] olc[dec] olc[zero] sel[Co] +XctrAND1i@0 net@12 fire[Co] ctrAND1in30 +XctrAND2i@0 olc[zero] net@12 olc[dec] ctrAND2in100 +Xnand2@0 sel[Co] do[ins] net@23 nand2-X_10 +XpredDri4@0 fire[Co] do[ins] predDri40 +Xwire90@0 net@23 net@12 wire90-431_3-layer_1-width_3 +.ENDS olcCount + +*** CELL: redFive:nand2n_sy{sch} +.SUBCKT nand2n_sy-X_6 ina inb out +Xnand2_sy@0 ina inb out nand2_sy-X_6 +.ENDS nand2n_sy-X_6 + +*** CELL: redFive:invLT{sch} +.SUBCKT invLT-X_3 in out +XNMOS@0 out in gnd NMOSx-X_6 +XPMOS@0 out in vdd PMOSx-X_3 +.ENDS invLT-X_3 + +*** CELL: driversM:predDri10wMC{sch} +.SUBCKT predDri10wMC in mc pred +XNMOSx@0 pred in gnd NMOSx-X_10 +XNMOSx@1 pred mc gnd NMOSx-X_4 +XinvLT@0 pred net@145 invLT-X_3 +Xpms3@0 pred in net@180 mc pms3-X_1 +Xwire90@0 net@180 net@145 wire90-106_7-layer_1-width_3 +.ENDS predDri10wMC + +*** CELL: driversM:sucDri10{sch} +.SUBCKT sucDri10 in succ +Xinv@1 succ net@94 inv-X_4 +Xinv@2 in net@110 inv-X_4 +Xnms2@0 succ net@117 net@109 nms2-X_2 +Xpms1@0 succ net@109 pms1-X_10 +Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3 +Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3 +.ENDS sucDri10 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-140_6-R_34_667m a b +Ccap@0 gnd net@14 0.516f +Ccap@1 gnd net@8 0.516f +Ccap@2 gnd net@11 0.516f +Rres@0 net@14 a 0.812 +Rres@1 net@11 net@14 1.625 +Rres@2 b net@8 0.812 +Rres@3 net@8 net@11 1.625 +.ENDS wire-C_0_011f-140_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-140_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-140_6-R_34_667m +.ENDS wire90-140_6-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-144_3-R_34_667m a b +Ccap@0 gnd net@14 0.529f +Ccap@1 gnd net@8 0.529f +Ccap@2 gnd net@11 0.529f +Rres@0 net@14 a 0.834 +Rres@1 net@11 net@14 1.667 +Rres@2 b net@8 0.834 +Rres@3 net@8 net@11 1.667 +.ENDS wire-C_0_011f-144_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-144_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-144_3-R_34_667m +.ENDS wire90-144_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-215_9-R_34_667m a b +Ccap@0 gnd net@14 0.792f +Ccap@1 gnd net@8 0.792f +Ccap@2 gnd net@11 0.792f +Rres@0 net@14 a 1.247 +Rres@1 net@11 net@14 2.495 +Rres@2 b net@8 1.247 +Rres@3 net@8 net@11 2.495 +.ENDS wire-C_0_011f-215_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-215_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-215_9-R_34_667m +.ENDS wire90-215_9-layer_1-width_3 + +*** CELL: loopCountM:olcLoad{sch} +.SUBCKT olcLoad do[ins] doneLO[M] fire[zz] mc olc[load] sel[Ld] sel[rD] +XctrAND3i@2 net@983 net@981 net@979 olc[load] ctrAND3in100A +Xinv@28 net@905 net@908 inv-X_5 +Xinv@30 sel[rD] net@976 inv-X_5 +Xinv@32 net@1032 net@1057 inv-X_5 +Xinv@34 net@913 inv@34_out inv-X_10 +XinvI@7 net@929 net@913 inv-X_5 +XinvI@8 net@1046 net@937 inv-X_10 +XinvI@11 net@908 invI@11_out inv-X_10 +Xnand2@5 sel[Ld] do[ins] net@956 nand2-X_5 +Xnand2@7 net@1035 do[2] net@1033 nand2-X_5 +Xnand2n_s@1 doneLO[M] net@908 fire[zz] nand2n_sy-X_6 +XpredDri1@0 net@979 mc do[2] predDri10wMC +XpredDri4@0 net@1032 do[ins] predDri40 +XsucDri10@1 olc[load] do[2] sucDri10 +Xwire90@17 net@1033 net@929 wire90-431_3-layer_1-width_3 +Xwire90@25 net@956 net@979 wire90-140_6-layer_1-width_3 +Xwire90@39 net@1032 net@937 wire90-144_3-layer_1-width_3 +Xwire90@42 net@913 net@905 wire90-215_9-layer_1-width_3 +Xwire90@48 net@976 net@981 wire90-431_3-layer_1-width_3 +Xwire90@50 net@983 do[2] wire90-431_3-layer_1-width_3 +Xwire90@51 net@1035 net@1057 wire90-431_3-layer_1-width_3 +Xwire90@52 net@908 net@1046 wire90-215_9-layer_1-width_3 +.ENDS olcLoad + +*** CELL: loopCountM:loadORcount{sch} +.SUBCKT loadORcount do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load] mc ++olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] sel[Co] sel[Ld] sel[rD] +XilcLoad@0 do[ins] ilc[load] sel[Ld] sel[rD] ilcLoad +XolcContr@1 net@885 net@880 flag[D][clr] flag[D][set] olc[zero] olc[zoo] s[1] ++s[2] olcControlD +XolcCount@0 do[ins] net@883 olc[dec] olc[zero] sel[Co] olcCount +XolcLoad@0 do[ins] doneLO[M] net@882 mc olc[load] sel[Ld] sel[rD] olcLoad +Xwire90@0 net@882 net@880 wire90-431_3-layer_1-width_3 +Xwire90@1 net@885 net@883 wire90-431_3-layer_1-width_3 +.ENDS loadORcount + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b +Ccap@0 gnd net@14 6.469f +Ccap@1 gnd net@8 6.469f +Ccap@2 gnd net@11 6.469f +Rres@0 net@14 a 10.194 +Rres@1 net@11 net@14 20.389 +Rres@2 b net@8 10.194 +Rres@3 net@8 net@11 20.389 +.ENDS wire-C_0_011f-1764_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1764_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m +.ENDS wire90-1764_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b +Ccap@0 gnd net@14 5.036f +Ccap@1 gnd net@8 5.036f +Ccap@2 gnd net@11 5.036f +Rres@0 net@14 a 7.935 +Rres@1 net@11 net@14 15.87 +Rres@2 b net@8 7.935 +Rres@3 net@8 net@11 15.87 +.ENDS wire-C_0_011f-1373_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1373_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m +.ENDS wire90-1373_4-layer_1-width_3 + +*** CELL: loopCountM:olcEven{sch} +.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2] ++inLO[4] inLO[6] load[T] +Xinv@2 count[T] net@210 inv-X_30 +Xinv@3 load[T] net@211 inv-X_30 +XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB +XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB +XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB +Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3 +Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3 .ENDS olcEven *** CELL: loopCountM:olcOdd{sch} @@ -7458,388 +7943,6 @@ Xwire90@4 wire90@4_a do[5] wire90-554_3-layer_1-width_3 Xwire90@5 wire90@5_a do[6] wire90-463_3-layer_1-width_3 .ENDS olc -*** CELL: centersJ:ctrAND2in100{sch} -.SUBCKT ctrAND2in100 inA inB out -Xinv@9 net@163 net@161 inv-X_30 -XinvI@1 net@162 out inv-X_100 -Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10 -Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3 -Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3 -.ENDS ctrAND2in100 - -*** CELL: centersJ:ctrAND3in30B{sch} -.SUBCKT ctrAND3in30B inA inB inC out -Xinv@4 inC net@30 inv-X_5 -Xinv@5 net@9 out inv-X_30 -Xnand2LT_@0 net@15 net@19 net@27 nand2LT_sy-X_10 -Xnor2n_sy@0 inA inB net@6 nor2n_sy-X_5 -Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3 -Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3 -Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3 -.ENDS ctrAND3in30B - -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_1 d g s -MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2' -+DELVTO='AVT0P/sqrt(6*2)' -.ENDS PMOSx-X_1 - -*** CELL: redFive:nms2{sch} -.SUBCKT nms2-X_1 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_2 -XNMOS@1 net@0 g gnd NMOSx-X_2 -.ENDS nms2-X_1 - -*** CELL: redFive:nand2{sch} -.SUBCKT nand2-X_1 ina inb out -XPMOS@0 out ina vdd PMOSx-X_1 -XPMOS@1 out inb vdd PMOSx-X_1 -Xnms2@0 out ina inb nms2-X_1 -.ENDS nand2-X_1 - -*** CELL: redFive:nms2{sch} -.SUBCKT nms2-X_2_5 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_5 -XNMOS@1 net@0 g gnd NMOSx-X_5 -.ENDS nms2-X_2_5 - -*** CELL: redFive:nms2_sy{sch} -.SUBCKT nms2_sy-X_5 d g g2 -Xnms2@0 d g g2 nms2-X_2_5 -Xnms2@1 d g2 g nms2-X_2_5 -.ENDS nms2_sy-X_5 - -*** CELL: redFive:nand2_sy{sch} -.SUBCKT nand2_sy-X_5 ina inb out -XPMOS@0 out inb vdd PMOSx-X_5 -XPMOS@1 out ina vdd PMOSx-X_5 -Xnms2_sy@0 out ina inb nms2_sy-X_5 -.ENDS nand2_sy-X_5 - -*** CELL: redFive:nand2n_sy{sch} -.SUBCKT nand2n_sy-X_5 ina inb out -Xnand2_sy@0 ina inb out nand2_sy-X_5 -.ENDS nand2n_sy-X_5 - -*** CELL: redFive:invLT{sch} -.SUBCKT invLT-X_3 in out -XNMOS@0 out in gnd NMOSx-X_6 -XPMOS@0 out in vdd PMOSx-X_3 -.ENDS invLT-X_3 - -*** CELL: driversL:predDri10wMC{sch} -.SUBCKT predDri10wMC in mc pred -XNMOSx@0 pred in gnd NMOSx-X_10 -XNMOSx@1 pred mc gnd NMOSx-X_4 -XinvLT@0 pred net@145 invLT-X_3 -Xpms3@0 pred in net@180 mc pms3-X_1 -Xwire90@0 net@180 net@145 wire90-106_7-layer_1-width_3 -.ENDS predDri10wMC - -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_2_5 d g s -MPMOSf@0 d g s vdd pch W='15*(1+ABP/sqrt(15*2))' L='2' -+DELVTO='AVT0P/sqrt(15*2)' -.ENDS PMOSx-X_2_5 - -*** CELL: redFive:nand2{sch} -.SUBCKT nand2-X_2_5 ina inb out -XPMOS@0 out ina vdd PMOSx-X_2_5 -XPMOS@1 out inb vdd PMOSx-X_2_5 -Xnms2@0 out ina inb nms2-X_2_5 -.ENDS nand2-X_2_5 - -*** CELL: driversL:sucANDdri10{sch} -.SUBCKT sucANDdri10 inA inB succ -XPMOSx@0 succ net@51 vdd PMOSx-X_10 -Xinv@0 succ net@71 inv-X_4 -Xnand2@0 inA inB net@67 nand2-X_2_5 -Xnms2@0 succ net@75 net@51 nms2-X_2 -Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3 -Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3 -.ENDS sucANDdri10 - -*** CELL: driversL:sucDri10{sch} -.SUBCKT sucDri10 in succ -Xinv@1 succ net@94 inv-X_4 -Xinv@2 in net@110 inv-X_4 -Xnms2@0 succ net@117 net@109 nms2-X_2 -Xpms1@0 succ net@109 pms1-X_10 -Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3 -Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3 -.ENDS sucDri10 - -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_3_999 d g s -MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2' -+DELVTO='AVT0N/sqrt(11.997*2)' -.ENDS NMOSx-X_3_999 - -*** CELL: redFive:nms3{sch} -.SUBCKT nms3-X_1_333 d g g2 g3 -XNMOS@0 d g3 net@6 NMOSx-X_3_999 -XNMOS@1 net@7 g gnd NMOSx-X_3_999 -XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999 -.ENDS nms3-X_1_333 - -*** CELL: driversL:sucDri20or{sch} -.SUBCKT sucDri20or inA inB succ -Xinv@1 succ net@94 inv-X_4 -Xnms3b@0 succ net@142 inB inA nms3-X_1_333 -Xpms1@0 succ inA pms1-X_20 -Xpms1@1 succ inB pms1-X_20 -Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3 -.ENDS sucDri20or - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-405-R_34_667m a b -Ccap@0 gnd net@14 1.485f -Ccap@1 gnd net@8 1.485f -Ccap@2 gnd net@11 1.485f -Rres@0 net@14 a 2.34 -Rres@1 net@11 net@14 4.68 -Rres@2 b net@8 2.34 -Rres@3 net@8 net@11 4.68 -.ENDS wire-C_0_011f-405-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-405-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-405-R_34_667m -.ENDS wire90-405-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-472_9-R_34_667m a b -Ccap@0 gnd net@14 1.734f -Ccap@1 gnd net@8 1.734f -Ccap@2 gnd net@11 1.734f -Rres@0 net@14 a 2.732 -Rres@1 net@11 net@14 5.465 -Rres@2 b net@8 2.732 -Rres@3 net@8 net@11 5.465 -.ENDS wire-C_0_011f-472_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-472_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-472_9-R_34_667m -.ENDS wire90-472_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-346_7-R_34_667m a b -Ccap@0 gnd net@14 1.271f -Ccap@1 gnd net@8 1.271f -Ccap@2 gnd net@11 1.271f -Rres@0 net@14 a 2.003 -Rres@1 net@11 net@14 4.006 -Rres@2 b net@8 2.003 -Rres@3 net@8 net@11 4.006 -.ENDS wire-C_0_011f-346_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-346_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-346_7-R_34_667m -.ENDS wire90-346_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-438_9-R_34_667m a b -Ccap@0 gnd net@14 1.609f -Ccap@1 gnd net@8 1.609f -Ccap@2 gnd net@11 1.609f -Rres@0 net@14 a 2.536 -Rres@1 net@11 net@14 5.072 -Rres@2 b net@8 2.536 -Rres@3 net@8 net@11 5.072 -.ENDS wire-C_0_011f-438_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-438_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-438_9-R_34_667m -.ENDS wire90-438_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-143_2-R_34_667m a b -Ccap@0 gnd net@14 0.525f -Ccap@1 gnd net@8 0.525f -Ccap@2 gnd net@11 0.525f -Rres@0 net@14 a 0.827 -Rres@1 net@11 net@14 1.655 -Rres@2 b net@8 0.827 -Rres@3 net@8 net@11 1.655 -.ENDS wire-C_0_011f-143_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-143_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-143_2-R_34_667m -.ENDS wire90-143_2-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-144_3-R_34_667m a b -Ccap@0 gnd net@14 0.529f -Ccap@1 gnd net@8 0.529f -Ccap@2 gnd net@11 0.529f -Rres@0 net@14 a 0.834 -Rres@1 net@11 net@14 1.667 -Rres@2 b net@8 0.834 -Rres@3 net@8 net@11 1.667 -.ENDS wire-C_0_011f-144_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-144_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-144_3-R_34_667m -.ENDS wire90-144_3-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-431_3-R_34_667m a b -Ccap@0 gnd net@14 1.581f -Ccap@1 gnd net@8 1.581f -Ccap@2 gnd net@11 1.581f -Rres@0 net@14 a 2.492 -Rres@1 net@11 net@14 4.984 -Rres@2 b net@8 2.492 -Rres@3 net@8 net@11 4.984 -.ENDS wire-C_0_011f-431_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-431_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-431_3-R_34_667m -.ENDS wire90-431_3-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-485_9-R_34_667m a b -Ccap@0 gnd net@14 1.782f -Ccap@1 gnd net@8 1.782f -Ccap@2 gnd net@11 1.782f -Rres@0 net@14 a 2.807 -Rres@1 net@11 net@14 5.615 -Rres@2 b net@8 2.807 -Rres@3 net@8 net@11 5.615 -.ENDS wire-C_0_011f-485_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-485_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-485_9-R_34_667m -.ENDS wire90-485_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-215_9-R_34_667m a b -Ccap@0 gnd net@14 0.792f -Ccap@1 gnd net@8 0.792f -Ccap@2 gnd net@11 0.792f -Rres@0 net@14 a 1.247 -Rres@1 net@11 net@14 2.495 -Rres@2 b net@8 1.247 -Rres@3 net@8 net@11 2.495 -.ENDS wire-C_0_011f-215_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-215_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-215_9-R_34_667m -.ENDS wire90-215_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-140_6-R_34_667m a b -Ccap@0 gnd net@14 0.516f -Ccap@1 gnd net@8 0.516f -Ccap@2 gnd net@11 0.516f -Rres@0 net@14 a 0.812 -Rres@1 net@11 net@14 1.625 -Rres@2 b net@8 0.812 -Rres@3 net@8 net@11 1.625 -.ENDS wire-C_0_011f-140_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-140_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-140_6-R_34_667m -.ENDS wire90-140_6-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-127_4-R_34_667m a b -Ccap@0 gnd net@14 0.467f -Ccap@1 gnd net@8 0.467f -Ccap@2 gnd net@11 0.467f -Rres@0 net@14 a 0.736 -Rres@1 net@11 net@14 1.472 -Rres@2 b net@8 0.736 -Rres@3 net@8 net@11 1.472 -.ENDS wire-C_0_011f-127_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-127_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-127_4-R_34_667m -.ENDS wire90-127_4-layer_1-width_3 - -*** CELL: loopCountM:olcControl{sch} -.SUBCKT olcControl Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] -+ilc[load] mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3] -XctrAND1i@4 net@547 fire[Co] ctrAND1in30 -XctrAND2i@5 olc[zero] net@547 olc[dec] ctrAND2in100 -XctrAND2i@9 net@348 net@340 olc[load] ctrAND2in100 -XctrAND2i@10 not[Ld] net@634 ilc[load] ctrAND2in100 -XctrAND3i@0 net@821 net@823 not[Ld] net@612 ctrAND3in30B -Xinv@6 olc[zoo] net@180 inv-X_5 -Xinv@7 olc[zero] net@184 inv-X_5 -Xinv@14 do[Co] net@386 inv-X_10 -Xinv@18 flag[D][set] net@535 inv-X_5 -Xinv@19 flag[D][clr] net@539 inv-X_5 -Xinv@20 do[Ld] net@576 inv-X_10 -Xinv@21 Dvoid net@605 inv-X_5 -Xinv@22 net@632 net@635 inv-X_5 -Xinv@25 do[zz] net@783 inv-X_5 -Xinv@26 net@887 net@893 inv-X_10 -Xinv@27 do[reD] net@885 inv-X_5 -Xinv@28 net@905 net@907 inv-X_10 -XinvI@2 net@538 s[3] inv-X_10 -XinvI@3 net@534 s[2] inv-X_10 -XinvI@4 not[Ld] s[1] inv-X_10 -XinvI@6 net@940 net@889 inv-X_5 -XinvI@7 net@929 net@913 inv-X_5 -XinvI@8 net@907 net@936 inv-X_10 -XinvI@9 net@893 net@938 inv-X_10 -Xnand2@0 net@288 fire[Co] net@286 nand2-X_5 -Xnand2@1 net@289 fire[zz] net@284 nand2-X_5 -Xnand2@2 olc[zoo] net@728 net@279 nand2-X_5 -Xnand2@3 olc[zero] net@926 net@281 nand2-X_5 -Xnand2@4 do[Ld] do[2] net@944 nand2-X_1 -Xnand2n_s@1 net@891 net@909 fire[zz] nand2n_sy-X_5 -XpredDri1@0 net@340 mc do[2] predDri10wMC -XpredDri1@1 not[Ld] mc net@632 predDri10wMC -XpredDri1@2 not[Ld] mc do[zz] predDri10wMC -XpredDri2@2 fire[Co] mc do[Co] predDri20wMC -XpredDri2@3 net@946 mc do[reD] predDri20wMC -XpredORdr@1 ilc[load] net@924 mc do[Ld] predORdri20wMC -XsucANDdr@2 Dvoid net@612 do[zz] sucANDdri10 -XsucANDdr@3 net@653 net@638 net@632 sucANDdri10 -XsucDri10@0 olc[load] do[2] sucDri10 -XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or -XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or -Xwire90@9 net@281 net@422 wire90-405-layer_1-width_3 -Xwire90@10 net@279 net@426 wire90-472_9-layer_1-width_3 -Xwire90@11 net@286 net@428 wire90-346_7-layer_1-width_3 -Xwire90@12 net@284 net@424 wire90-438_9-layer_1-width_3 -Xwire90@13 net@180 net@288 wire90-143_2-layer_1-width_3 -Xwire90@14 net@184 net@289 wire90-144_3-layer_1-width_3 -Xwire90@17 net@783 net@340 wire90-431_3-layer_1-width_3 -Xwire90@19 net@386 net@547 wire90-485_9-layer_1-width_3 -Xwire90@22 net@885 net@940 wire90-215_9-layer_1-width_3 -Xwire90@23 net@535 net@534 wire90-140_6-layer_1-width_3 -Xwire90@24 net@539 net@538 wire90-140_6-layer_1-width_3 -Xwire90@25 net@576 not[Ld] wire90-140_6-layer_1-width_3 -Xwire90@26 net@638 net@612 wire90-127_4-layer_1-width_3 -Xwire90@27 net@653 net@605 wire90-127_4-layer_1-width_3 -Xwire90@28 net@634 net@635 wire90-127_4-layer_1-width_3 -Xwire90@31 net@823 net@632 wire90-140_6-layer_1-width_3 -Xwire90@32 net@821 do[zz] wire90-140_6-layer_1-width_3 -Xwire90@36 net@348 do[2] wire90-431_3-layer_1-width_3 -Xwire90@37 fire[Co] net@728 wire90-472_9-layer_1-width_3 -Xwire90@39 net@924 net@936 wire90-144_3-layer_1-width_3 -Xwire90@40 net@889 net@887 wire90-215_9-layer_1-width_3 -Xwire90@41 net@891 net@893 wire90-215_9-layer_1-width_3 -Xwire90@42 net@913 net@905 wire90-215_9-layer_1-width_3 -Xwire90@43 net@909 net@907 wire90-215_9-layer_1-width_3 -Xwire90@45 net@926 fire[zz] wire90-215_9-layer_1-width_3 -Xwire90@46 net@929 net@944 wire90-215_9-layer_1-width_3 -Xwire90@47 net@938 net@946 wire90-215_9-layer_1-width_3 -.ENDS olcControl - *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-1022_9-R_34_667m a b Ccap@0 gnd net@14 3.751f @@ -7985,16 +8088,16 @@ Xwire@0 a b wire-C_0_011f-1638_1-R_34_667m .ENDS wire90-1638_1-layer_1-width_3 *** CELL: loopCountM:olcWcont{sch} -.SUBCKT olcWcont Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] -+ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sin -+sout +.SUBCKT olcWcont do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load] ++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sel[Co] sel[Ld] ++sel[rD] sin sout +XloadORco@0 do[ins] doneLO[M] flag[D][clr] flag[D][set] ilc[load] mc olc[dec] ++olc[load] olc[zero] olc[zoo] s[1] s[2] sel[Co] sel[Ld] sel[rD] loadORcount Xolc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2] +inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] olc -XolcContr@0 Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] ilc[load] -+mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3] olcControl +XscanEx2h@0 s[1] s[2] mc p1p p2p rd net@81 sout scanEx2h XscanEx3h@1 bitt[1] bitt[3] bitt[5] mc p1p p2p rd sin net@46 scanEx3h -XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@48 scanEx3h -XscanEx3h@3 s[3] s[2] s[1] mc p1p p2p rd net@48 sout scanEx3h +XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@81 scanEx3h Xwire90@1 olc[zero] wire90@1_b wire90-1022_9-layer_1-width_3 Xwire90@2 olc[zoo] wire90@2_b wire90-810_8-layer_1-width_3 Xwire90@3 olc[load] wire90@3_b wire90-4437_9-layer_1-width_3 @@ -8104,33 +8207,32 @@ Xwire@0 a b wire-C_0_011f-867_8-R_34_667m .ENDS wire90-867_8-layer_1-width_3 *** CELL: stagesM:outDockCenter{sch} -.SUBCKT outDockCenter bit[18] bit[19] bit[20] do[Lt] epi[torp] fire[M] -+fire[do] flag[A][clr] flag[A][set] flag[C][T] flag[D][clr] flag[D][set] -+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] in[1] in[2] in[3] -+in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] -+m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] -+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] -+m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[do] ps[skip] sel[Co] sel[Fl] -+sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] sir[1] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] sir[9] sor[1] succ[sf] +.SUBCKT outDockCenter do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set] ++flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] ++inLO[6] inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12] ++m1[1] m1[21] m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ++m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] ++m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ++pred[D] pred[T] ps[18] ps[19] ps[20] ps[21] ps[23] ps[24] ps[25] ps[26] ++ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] ++sir[9] sor[1] succ[sf] +XbitAssig@0 bitAssignments Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T] +m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] +sir[9] sir[3] sir[2] sir[5] sir[1] net@279 flags -XilcMoveO@0 bit[18] bit[19] do[Mv] do[Tp] do[reD] epi[torp] fire[M] -+flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] -+inLO[8] sir[9] sir[3] sir[2] pred[D] pred[T] sir[5] net@249 sor[1] succ[sf] -+ilcMoveOut +XilcMoveO@0 do[ins] net@293 epi[torp] fire[M] flag[D][set] ilc[load] inLO[1] ++inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] sir[9] sir[3] sir[2] pred[D] ++pred[T] sir[5] ps[18] ps[25] ps[19] ps[26] net@249 sor[1] succ[sf] ilcMoveOut XmuxForD@0 in[1] in[2] in[3] in[4] in[5] in[6] inLO[1] inLO[2] inLO[3] -+inLO[4] inLO[5] inLO[6] inLO[8] bit[20] muxForD -XohPredAl@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr] -+flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] -+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] -+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] -+sir[3] sir[2] ps[do] ps[skip] sir[5] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] -+sel[Tp] sel[rD] net@244 net@249 ohPredAll -XolcWcont@0 sel[rD] do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@165 -+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5] -+net@279 net@244 olcWcont ++inLO[4] inLO[5] inLO[6] inLO[8] ps[20] muxForD +XohPredAl@0 do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] ++flag[D][clr] flag[D][set] m1[22] m1[21] m1cate[1][F] m1cate[1][T] ++m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] ++m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] sir[3] sir[2] ++ps[do] ps[skip] sir[5] net@244 net@249 ohPredAll +XolcWcont@0 do[ins] doneLO[M] flag[D][clr] flag[D][set] net@165 inLO[1] ++inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5] ps[24] ++ps[23] ps[21] net@279 net@244 olcWcont Xtc[1] tranCap Xtc[2] tranCap Xtc[3] tranCap @@ -8152,25 +8254,10 @@ Xwire90@8 wire90@8_a flag[B][clr] wire90-3611-layer_1-width_3 Xwire90@9 wire90@9_a flag[D][set] wire90-1850-layer_1-width_3 Xwire90@10 wire90@10_a flag[D][clr] wire90-1852-layer_1-width_3 Xwire90@24 net@165 ilc[load] wire90-867_8-layer_1-width_3 +Xwire90@25 net@293 doneLO[M] wire90-867_8-layer_1-width_3 .ENDS outDockCenter *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-3405_8-R_34_667m a b -Ccap@0 gnd net@14 12.488f -Ccap@1 gnd net@8 12.488f -Ccap@2 gnd net@11 12.488f -Rres@0 net@14 a 19.678 -Rres@1 net@11 net@14 39.356 -Rres@2 b net@8 19.678 -Rres@3 net@8 net@11 39.356 -.ENDS wire-C_0_011f-3405_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-3405_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-3405_8-R_34_667m -.ENDS wire90-3405_8-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-5146_2-R_34_667m a b Ccap@0 gnd net@14 18.869f Ccap@1 gnd net@8 18.869f @@ -8283,35 +8370,31 @@ Xwire@0 a b wire-C_0_011f-3136_9-R_34_667m .ENDS wire90-3136_9-layer_1-width_3 *** CELL: stagesM:outDockPredStage{sch} -.SUBCKT outDockPredStage do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set] +.SUBCKT outDockPredStage do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set] +flag[C][T] flag[D][clr] flag[D][set] in[1] in[2] in[3] in[4] in[5] in[6] +m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] -+m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] -+m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] -+m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] -+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] -+m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] -+ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] -+ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] sor[1] succ[sf] -XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] ++m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[2] m1[3] m1[4] ++m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] ++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] ++m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ++ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2] ++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[sf] +XdockPSre@0 do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] +m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] -+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] -+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] -+inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] -+ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27] -+ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3] -+ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSre@0_take[1] dockPSreg -XoutDockC@0 ps[18] ps[19] ps[20] do[Lt] epi[torp] fire[M] net@6 flag[A][clr] -+flag[A][set] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] -+inLO[4] inLO[5] inLO[6] inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] -+m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] -+m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] -+m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] -+pred[D] pred[T] ps[do] ps[skip] m1[24] m1[22] m1[23] m1[27] m1[25] m1[26] -+m1[21] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] -+succ[sf] outDockCenter -Xwire90@0 net@6 net@39 wire90-3405_8-layer_1-width_3 ++m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3] ++inLO[4] inLO[5] inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ++ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSreg +XoutDockC@0 net@101 epi[torp] fire[M] flag[A][clr] flag[A][set] flag[C][T] ++flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] ++inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[21] ++m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] ++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] ++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] ++pred[T] ps[18] ps[19] ps[20] ps[21] ps[23] ps[24] ps[25] ps[26] ps[do] ++ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] ++sor[1] succ[sf] outDockCenter Xwire90@1 wire90@1_a inLO[1] wire90-5146_2-layer_1-width_3 Xwire90@2 wire90@2_a inLO[2] wire90-5054_2-layer_1-width_3 Xwire90@3 wire90@3_a inLO[3] wire90-4771_5-layer_1-width_3 @@ -8319,6 +8402,7 @@ Xwire90@4 wire90@4_a inLO[4] wire90-4764_9-layer_1-width_3 Xwire90@5 wire90@5_a inLO[5] wire90-4475_8-layer_1-width_3 Xwire90@6 wire90@6_a inLO[6] wire90-4496_1-layer_1-width_3 Xwire90@7 wire90@7_a inLO[8] wire90-3136_9-layer_1-width_3 +Xwire90@8 net@101 do[ins] wire90-5146_2-layer_1-width_3 .ENDS outDockPredStage *** CELL: orangeTSMC090nm:wire{sch} @@ -8354,20 +8438,212 @@ Xwire@0 a b wire-C_0_011f-3539_8-R_34_667m .ENDS wire90-3539_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1810_5-R_34_667m a b -Ccap@0 gnd net@14 6.639f -Ccap@1 gnd net@8 6.639f -Ccap@2 gnd net@11 6.639f -Rres@0 net@14 a 10.461 -Rres@1 net@11 net@14 20.921 -Rres@2 b net@8 10.461 -Rres@3 net@8 net@11 20.921 -.ENDS wire-C_0_011f-1810_5-R_34_667m +.SUBCKT wire-C_0_011f-6608_3-R_34_667m a b +Ccap@0 gnd net@14 24.23f +Ccap@1 gnd net@8 24.23f +Ccap@2 gnd net@11 24.23f +Rres@0 net@14 a 38.181 +Rres@1 net@11 net@14 76.363 +Rres@2 b net@8 38.181 +Rres@3 net@8 net@11 76.363 +.ENDS wire-C_0_011f-6608_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1810_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1810_5-R_34_667m -.ENDS wire90-1810_5-layer_1-width_3 +.SUBCKT wire90-6608_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-6608_3-R_34_667m +.ENDS wire90-6608_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1466_1-R_34_667m a b +Ccap@0 gnd net@14 5.376f +Ccap@1 gnd net@8 5.376f +Ccap@2 gnd net@11 5.376f +Rres@0 net@14 a 8.471 +Rres@1 net@11 net@14 16.942 +Rres@2 b net@8 8.471 +Rres@3 net@8 net@11 16.942 +.ENDS wire-C_0_011f-1466_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1466_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1466_1-R_34_667m +.ENDS wire90-1466_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1632_5-R_34_667m a b +Ccap@0 gnd net@14 5.986f +Ccap@1 gnd net@8 5.986f +Ccap@2 gnd net@11 5.986f +Rres@0 net@14 a 9.432 +Rres@1 net@11 net@14 18.864 +Rres@2 b net@8 9.432 +Rres@3 net@8 net@11 18.864 +.ENDS wire-C_0_011f-1632_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1632_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1632_5-R_34_667m +.ENDS wire90-1632_5-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1066_4-R_34_667m a b +Ccap@0 gnd net@14 3.91f +Ccap@1 gnd net@8 3.91f +Ccap@2 gnd net@11 3.91f +Rres@0 net@14 a 6.161 +Rres@1 net@11 net@14 12.323 +Rres@2 b net@8 6.161 +Rres@3 net@8 net@11 12.323 +.ENDS wire-C_0_011f-1066_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1066_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1066_4-R_34_667m +.ENDS wire90-1066_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1232_5-R_34_667m a b +Ccap@0 gnd net@14 4.519f +Ccap@1 gnd net@8 4.519f +Ccap@2 gnd net@11 4.519f +Rres@0 net@14 a 7.121 +Rres@1 net@11 net@14 14.242 +Rres@2 b net@8 7.121 +Rres@3 net@8 net@11 14.242 +.ENDS wire-C_0_011f-1232_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1232_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1232_5-R_34_667m +.ENDS wire90-1232_5-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1106_7-R_34_667m a b +Ccap@0 gnd net@14 4.058f +Ccap@1 gnd net@8 4.058f +Ccap@2 gnd net@11 4.058f +Rres@0 net@14 a 6.394 +Rres@1 net@11 net@14 12.789 +Rres@2 b net@8 6.394 +Rres@3 net@8 net@11 12.789 +.ENDS wire-C_0_011f-1106_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1106_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1106_7-R_34_667m +.ENDS wire90-1106_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1242_8-R_34_667m a b +Ccap@0 gnd net@14 4.557f +Ccap@1 gnd net@8 4.557f +Ccap@2 gnd net@11 4.557f +Rres@0 net@14 a 7.181 +Rres@1 net@11 net@14 14.361 +Rres@2 b net@8 7.181 +Rres@3 net@8 net@11 14.361 +.ENDS wire-C_0_011f-1242_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1242_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1242_8-R_34_667m +.ENDS wire90-1242_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1260_9-R_34_667m a b +Ccap@0 gnd net@14 4.623f +Ccap@1 gnd net@8 4.623f +Ccap@2 gnd net@11 4.623f +Rres@0 net@14 a 7.285 +Rres@1 net@11 net@14 14.57 +Rres@2 b net@8 7.285 +Rres@3 net@8 net@11 14.57 +.ENDS wire-C_0_011f-1260_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1260_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1260_9-R_34_667m +.ENDS wire90-1260_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1327_2-R_34_667m a b +Ccap@0 gnd net@14 4.866f +Ccap@1 gnd net@8 4.866f +Ccap@2 gnd net@11 4.866f +Rres@0 net@14 a 7.668 +Rres@1 net@11 net@14 15.337 +Rres@2 b net@8 7.668 +Rres@3 net@8 net@11 15.337 +.ENDS wire-C_0_011f-1327_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1327_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1327_2-R_34_667m +.ENDS wire90-1327_2-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1283_7-R_34_667m a b +Ccap@0 gnd net@14 4.707f +Ccap@1 gnd net@8 4.707f +Ccap@2 gnd net@11 4.707f +Rres@0 net@14 a 7.417 +Rres@1 net@11 net@14 14.834 +Rres@2 b net@8 7.417 +Rres@3 net@8 net@11 14.834 +.ENDS wire-C_0_011f-1283_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1283_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1283_7-R_34_667m +.ENDS wire90-1283_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1456_1-R_34_667m a b +Ccap@0 gnd net@14 5.339f +Ccap@1 gnd net@8 5.339f +Ccap@2 gnd net@11 5.339f +Rres@0 net@14 a 8.413 +Rres@1 net@11 net@14 16.826 +Rres@2 b net@8 8.413 +Rres@3 net@8 net@11 16.826 +.ENDS wire-C_0_011f-1456_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1456_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1456_1-R_34_667m +.ENDS wire90-1456_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1427_2-R_34_667m a b +Ccap@0 gnd net@14 5.233f +Ccap@1 gnd net@8 5.233f +Ccap@2 gnd net@11 5.233f +Rres@0 net@14 a 8.246 +Rres@1 net@11 net@14 16.492 +Rres@2 b net@8 8.246 +Rres@3 net@8 net@11 16.492 +.ENDS wire-C_0_011f-1427_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1427_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1427_2-R_34_667m +.ENDS wire90-1427_2-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1544_9-R_34_667m a b +Ccap@0 gnd net@14 5.665f +Ccap@1 gnd net@8 5.665f +Ccap@2 gnd net@11 5.665f +Rres@0 net@14 a 8.926 +Rres@1 net@11 net@14 17.852 +Rres@2 b net@8 8.926 +Rres@3 net@8 net@11 17.852 +.ENDS wire-C_0_011f-1544_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1544_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1544_9-R_34_667m +.ENDS wire90-1544_9-layer_1-width_3 *** CELL: stageGroupsM:outM1PredLit{sch} .SUBCKT outM1PredLit dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] @@ -8399,10 +8675,9 @@ XlitDandP@0 net@89 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] +dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] +dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] +dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] -+dsD[8] dsD[9] net@90 net@79 ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] -+ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] -+ps[9] signalBitFromInboundSwitchFabric net@48[8] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] litDandP ++dsD[8] dsD[9] net@90 flag[C] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ++ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ++ps[8] ps[9] signalBitFromInboundSwitchFabric succ[D] succ[T] litDandP XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] +m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] +m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] @@ -8415,20 +8690,31 @@ XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] +ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] +sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@47[8] +succ[m1] take[m1] mOneDockStage -XoutDockP@0 net@91 epi[torp] fire[M] flag[A][clr] flag[A][set] net@82 +XoutDockP@0 do[ins] epi[torp] fire[M] flag[A][clr] flag[A][set] net@82 +flag[D][clr] flag[D][set] dsD[1] dsD[2] dsD[3] dsD[4] dsD[5] dsD[6] m1[10] +m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] -+m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] -+m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] -+m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] -+m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] -+m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] -+ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] -+ps[9] ps[do] ps[skip] net@47[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] net@48[8] succ[D] outDockPredStage -Xwire90@0 net@79 net@82 wire90-2993_2-layer_1-width_3 ++m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[2] m1[3] m1[4] m1[5] ++m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] ++m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] ++m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ++ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[27] ps[2] ps[3] ps[4] ++ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] net@47[8] sir[2] sir[3] sir[4] ++sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] outDockPredStage +Xwire90@0 flag[C] net@82 wire90-2993_2-layer_1-width_3 Xwire90@1 net@90 fire[M] wire90-3539_8-layer_1-width_3 -Xwire90@2 net@89 net@91 wire90-1810_5-layer_1-width_3 +Xwire90@2 net@89 do[ins] wire90-6608_3-layer_1-width_3 +Xwire90@3 wire90@3_a m1cate[1][T] wire90-1466_1-layer_1-width_3 +Xwire90@4 wire90@4_a m1cate[1][F] wire90-1632_5-layer_1-width_3 +Xwire90@5 wire90@5_a m1cate[2][T] wire90-1066_4-layer_1-width_3 +Xwire90@6 wire90@6_a m1cate[2][F] wire90-1232_5-layer_1-width_3 +Xwire90@7 wire90@7_a m1cate[3][T] wire90-1106_7-layer_1-width_3 +Xwire90@8 wire90@8_a m1cate[3][F] wire90-1242_8-layer_1-width_3 +Xwire90@9 wire90@9_a m1cate[4][T] wire90-1260_9-layer_1-width_3 +Xwire90@10 wire90@10_a m1cate[4][F] wire90-1327_2-layer_1-width_3 +Xwire90@11 wire90@11_a m1cate[5][T] wire90-1283_7-layer_1-width_3 +Xwire90@12 wire90@12_a m1cate[5][F] wire90-1456_1-layer_1-width_3 +Xwire90@13 wire90@13_a m1cate[6][T] wire90-1427_2-layer_1-width_3 +Xwire90@14 wire90@14_a m1cate[6][F] wire90-1544_9-layer_1-width_3 .ENDS outM1PredLit *** CELL: orangeTSMC090nm:wire{sch} @@ -8570,7 +8856,7 @@ XctrAND3i@0 succ[A] succ[B] net@163 fire ctrAND3in100LT XdataDriv@0 tok fire take dataDriver60 Xinv@0 pred net@240 inv-X_10 XinvI@0 net@240 s[1] inv-X_10 -XpredDri6@0 fire mc pred driversJ__predDri60wMC +XpredDri6@1 fire mc pred predDri60wMC XsucANDdr@2 to[A] fire succ[A] sucANDdri60 XsucANDdr@3 to[B] fire succ[B] sucANDdri60 Xtc[1] tranCap diff --git a/testCode/marina.v b/testCode/marina.v index 40c3340..9fc4dd2 100644 --- a/testCode/marina.v +++ b/testCode/marina.v @@ -1,7 +1,7 @@ /* Verilog for cell 'marinaOut{sch}' from library 'aMarinaM' */ /* Created on Mon Nov 17, 2008 08:47:24 */ /* Last revised on Mon Mar 30, 2009 06:59:15 */ -/* Written on Wed Apr 29, 2009 17:24:11 by Electric VLSI Design System, version 8.08k */ +/* Written on Thu Apr 30, 2009 17:07:05 by Electric VLSI Design System, version 8.08k */ module orangeTSMC090nm__wire(a); input a; @@ -4752,8 +4752,8 @@ module moveM__moveRepeat(do_ins_, in_D_, in_T_, sel_Di_, sel_Mv_, sel_Ti_, endmodule /* moveM__moveRepeat */ module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_, - pred_T_, sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, succ_sf_, do_reD_, fire_M_, - flag_D__set_, s, winLO_M_); + pred_T_, sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, succ_sf_, doneLO_M_, + fire_M_, flag_D__set_, s, winLO_M_); input do_ins_; input epi_torp_; input ilc_do_; @@ -4766,7 +4766,7 @@ module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_, input sel_Ti_; input sel_Tp_; input succ_sf_; - output do_reD_; + output doneLO_M_; output fire_M_; output flag_D__set_; output [1:3] s; @@ -4774,8 +4774,8 @@ module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_, supply1 vdd; supply0 gnd; - wire done_M_, fire_T_, net_194, net_200, net_201, net_205, net_206, net_220; - wire net_227, net_29, net_326; + wire fire_T_, net_194, net_200, net_201, net_205, net_206, net_220, net_227; + wire net_250, net_29, net_326; /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) inv_9 (net_326, fire_T_); @@ -4793,6 +4793,9 @@ module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_, not (strong0, strong1) #(100) inv_15 (net_29, epi_torp_); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ + not (strong0, strong1) #(100) inv_16 (doneLO_M_, net_250); + // end Verilog_template + /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) invI_9 (s[1], net_194); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ @@ -4811,7 +4814,7 @@ module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_, /* begin Verilog_template for redFive:nand2{sch}*/ nand (strong0, strong1) #(100) nand2_3 (net_205, ilc_do_, sel_Ti_); // end Verilog_template - redFive__nor2n nor2n_1(.ina(ilc_mo_), .inb(winLO_M_), .out(done_M_)); + redFive__nor2n nor2n_1(.ina(ilc_mo_), .inb(winLO_M_), .out(net_250)); redFive__nor2n nor2n_5(.ina(net_206), .inb(winLO_M_), .out(net_201)); redFive__nor2n nor2n_6(.ina(net_205), .inb(winLO_M_), .out(net_200)); redFive__nor2n nor2n_7(.ina(net_220), .inb(winLO_M_), .out(fire_M_)); @@ -4819,15 +4822,14 @@ module moveM__moveOut(do_ins_, epi_torp_, ilc_do_, ilc_mo_, mc, pred_D_, driversM__predDri20wMC predDri2_0(.in(fire_T_), .mc(mc), .pred(epi_torp_)); driversM__predDri20wMC predDri2_3(.in(net_201), .mc(mc), .pred(pred_D_)); driversM__predDri20wMC predDri2_4(.in(net_200), .mc(mc), .pred(pred_T_)); - driversM__predDri40 predDri4_0(.in(done_M_), .pred(do_ins_)); + driversM__predDri40 predDri4_0(.in(net_250), .pred(do_ins_)); driversM__predDri40 predDri4_1(.in(fire_T_), .pred(do_ins_)); - driversM__sucDri20 sucDri20_0(.in(done_M_), .succ(do_reD_)); orangeTSMC090nm__wire90 wire90_9(.a(net_206)); orangeTSMC090nm__wire90 wire90_10(.a(net_220)); orangeTSMC090nm__wire90 wire90_11(.a(net_200)); orangeTSMC090nm__wire90 wire90_12(.a(net_201)); orangeTSMC090nm__wire90 wire90_13(.a(net_205)); - orangeTSMC090nm__wire90 wire90_15(.a(done_M_)); + orangeTSMC090nm__wire90 wire90_15(.a(net_250)); orangeTSMC090nm__wire90 wire90_16(.a(fire_T_)); orangeTSMC090nm__wire90 wire90_17(.a(net_326)); endmodule /* moveM__moveOut */ @@ -4895,7 +4897,7 @@ endmodule /* scanM__scanEx4h */ module moveM__ilcMoveOut(do_ins_, epi_torp_, ilc_load_, \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , \inLO[8] , pred_D_, pred_T_, - sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, sin, succ_sf_, do_reD_, fire_M_, + sel_Di_, sel_Mv_, sel_Ti_, sel_Tp_, sin, succ_sf_, doneLO_M_, fire_M_, flag_D__set_, sout, mc, p1p, p2p, rd); input do_ins_; input epi_torp_; @@ -4910,7 +4912,7 @@ module moveM__ilcMoveOut(do_ins_, epi_torp_, ilc_load_, \inLO[1] , \inLO[2] , input sel_Tp_; input sin; input succ_sf_; - output do_reD_; + output doneLO_M_; output fire_M_; output flag_D__set_; output sout; @@ -4934,7 +4936,7 @@ module moveM__ilcMoveOut(do_ins_, epi_torp_, ilc_load_, \inLO[1] , \inLO[2] , .ilc_do_(ilc_do_), .ilc_mo_(ilc_mo_), .mc(mc), .pred_D_(pred_D_), .pred_T_(pred_T_), .sel_Di_(sel_Di_), .sel_Mv_(sel_Mv_), .sel_Ti_(sel_Ti_), .sel_Tp_(sel_Tp_), .succ_sf_(succ_sf_), - .do_reD_(do_reD_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_), + .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_), .s(s[1:3]), .winLO_M_(ilc_decLO_)); scanM__scanEx1h scanEx1h_0(.dIn({s[3]}), .sin(net_84), .mc(mc), .sout(sout), .p1p(p1p), .p2p(p2p), .rd(rd)); @@ -5334,8 +5336,8 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_, supply1 vdd; supply0 gnd; - wire fire_both_, fire_skip_, net_11, net_151, net_19, net_200, net_41, net_46; - wire net_63, net_82, net_92; + wire fire_both_, fire_do_, fire_skip_, net_11, net_19, net_200, net_41; + wire net_46, net_63, net_82, net_92; wire [1:3] s; wiresL__bitAssignments bitAssig_0(); @@ -5343,7 +5345,7 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_, not (strong0, strong1) #(100) inv_1 (net_200, do_ins_); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ - not (strong0, strong1) #(100) invI_0 (net_151, net_82); + not (strong0, strong1) #(100) invI_0 (fire_do_, net_82); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) invI_1 (fire_skip_, net_63); @@ -5361,7 +5363,7 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_, predicateM__nand3in20sr nand3in2_1(.inA(net_46), .inB(net_41), .inC(net_11), .resetLO(net_19), .out(net_82)); redFive__nor2n_sy nor2n_sy_0(.ina(ps_skip_), .inb(ps_do_), .out(net_11)); - predicateM__ohPredDo ohPredDo_1(.fire_do_(net_151), .fire_skip_(fire_skip_), + predicateM__ohPredDo ohPredDo_1(.fire_do_(fire_do_), .fire_skip_(fire_skip_), .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), @@ -5390,7 +5392,7 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_, orangeTSMC090nm__wire90 wire90_7(.a(fire_skip_)); orangeTSMC090nm__wire90 wire90_9(.a(fire_both_)); orangeTSMC090nm__wire90 wire90_10(.a(net_200)); - orangeTSMC090nm__wire90 wire90_11(.a(net_151)); + orangeTSMC090nm__wire90 wire90_11(.a(fire_do_)); endmodule /* predicateM__ohPredAll */ module centersJ__ctrAND2in100(inA, inB, out); @@ -5570,10 +5572,10 @@ module driversM__sucDri10(in, succ); orangeTSMC090nm__wire90 wire90_1(.a(net_109)); endmodule /* driversM__sucDri10 */ -module loopCountM__olcLoad(do_ins_, do_reD_, mc, sel_Ld_, sel_rD_, fire_zz_, +module loopCountM__olcLoad(do_ins_, doneLO_M_, mc, sel_Ld_, sel_rD_, fire_zz_, olc_load_); input do_ins_; - input do_reD_; + input doneLO_M_; input mc; input sel_Ld_; input sel_rD_; @@ -5582,20 +5584,13 @@ module loopCountM__olcLoad(do_ins_, do_reD_, mc, sel_Ld_, sel_rD_, fire_zz_, supply1 vdd; supply0 gnd; - wire invI_10_out, invI_11_out, inv_33_out, inv_34_out, net_1035, net_885; - wire net_887, net_891, net_905, net_908, net_929, net_937, net_938, net_956; - wire net_976; + wire invI_11_out, inv_34_out, net_1035, net_905, net_908, net_929, net_937; + wire net_956, net_976; wire [2:2] do; centersJ__ctrAND3in100A ctrAND3i_2(.inA(do[2]), .inB(net_976), .inC(net_956), .out(olc_load_)); /* begin Verilog_template for redFive:inv{sch}*/ - not (strong0, strong1) #(100) inv_26 (net_891, net_887); - // end Verilog_template - /* begin Verilog_template for redFive:inv{sch}*/ - not (strong0, strong1) #(100) inv_27 (net_885, do_reD_); - // end Verilog_template - /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) inv_28 (net_908, net_905); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ @@ -5605,27 +5600,15 @@ module loopCountM__olcLoad(do_ins_, do_reD_, mc, sel_Ld_, sel_rD_, fire_zz_, not (strong0, strong1) #(100) inv_32 (net_1035, net_937); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ - not (strong0, strong1) #(100) inv_33 (inv_33_out, net_887); - // end Verilog_template - /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) inv_34 (inv_34_out, net_905); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ - not (strong0, strong1) #(100) invI_6 (net_887, net_885); - // end Verilog_template - /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) invI_7 (net_905, net_929); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) invI_8 (net_937, net_908); // end Verilog_template /* begin Verilog_template for redFive:inv{sch}*/ - not (strong0, strong1) #(100) invI_9 (net_938, net_891); - // end Verilog_template - /* begin Verilog_template for redFive:inv{sch}*/ - not (strong0, strong1) #(100) invI_10 (invI_10_out, net_891); - // end Verilog_template - /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) invI_11 (invI_11_out, net_908); // end Verilog_template /* begin Verilog_template for redFive:nand2{sch}*/ @@ -5634,30 +5617,26 @@ module loopCountM__olcLoad(do_ins_, do_reD_, mc, sel_Ld_, sel_rD_, fire_zz_, /* begin Verilog_template for redFive:nand2{sch}*/ nand (strong0, strong1) #(100) nand2_7 (net_929, net_1035, do[2]); // end Verilog_template - redFive__nand2n_sy nand2n_s_1(.ina(net_891), .inb(net_908), .out(fire_zz_)); + redFive__nand2n_sy nand2n_s_1(.ina(doneLO_M_), .inb(net_908), + .out(fire_zz_)); driversM__predDri10wMC predDri1_0(.in(net_956), .mc(mc), .pred(do[2])); - driversM__predDri20wMC predDri2_3(.in(net_938), .mc(mc), .pred(do_reD_)); driversM__predDri40 predDri4_0(.in(net_937), .pred(do_ins_)); driversM__sucDri10 sucDri10_1(.in(olc_load_), .succ(do[2])); orangeTSMC090nm__wire90 wire90_17(.a(net_929)); - orangeTSMC090nm__wire90 wire90_22(.a(net_885)); orangeTSMC090nm__wire90 wire90_25(.a(net_956)); orangeTSMC090nm__wire90 wire90_39(.a(net_937)); - orangeTSMC090nm__wire90 wire90_40(.a(net_887)); - orangeTSMC090nm__wire90 wire90_41(.a(net_891)); orangeTSMC090nm__wire90 wire90_42(.a(net_905)); - orangeTSMC090nm__wire90 wire90_47(.a(net_938)); orangeTSMC090nm__wire90 wire90_48(.a(net_976)); orangeTSMC090nm__wire90 wire90_50(.a(do[2])); orangeTSMC090nm__wire90 wire90_51(.a(net_1035)); orangeTSMC090nm__wire90 wire90_52(.a(net_908)); endmodule /* loopCountM__olcLoad */ -module loopCountM__loadORcount(do_ins_, do_reD_, mc, olc_zero_, olc_zoo_, +module loopCountM__loadORcount(do_ins_, doneLO_M_, mc, olc_zero_, olc_zoo_, sel_Co_, sel_Ld_, sel_rD_, flag_D__clr_, flag_D__set_, ilc_load_, olc_dec_, olc_load_, s); input do_ins_; - input do_reD_; + input doneLO_M_; input mc; input olc_zero_; input olc_zoo_; @@ -5682,8 +5661,8 @@ module loopCountM__loadORcount(do_ins_, do_reD_, mc, olc_zero_, olc_zoo_, .flag_D__set_(flag_D__set_), .s(s[1:2])); loopCountM__olcCount olcCount_0(.do_ins_(do_ins_), .olc_zero_(olc_zero_), .sel_Co_(sel_Co_), .fire_Co_(net_883), .olc_dec_(olc_dec_)); - loopCountM__olcLoad olcLoad_0(.do_ins_(do_ins_), .do_reD_(do_reD_), .mc(mc), - .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .fire_zz_(net_880), + loopCountM__olcLoad olcLoad_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_), + .mc(mc), .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .fire_zz_(net_880), .olc_load_(olc_load_)); orangeTSMC090nm__wire90 wire90_0(.a(net_880)); orangeTSMC090nm__wire90 wire90_1(.a(net_883)); @@ -5785,10 +5764,11 @@ module loopCountM__olc(inLO, olc_dec_, olc_load_, bitt, olc_zero_, olc_zoo_); orangeTSMC090nm__wire90 wire90_5(.a(do[6])); endmodule /* loopCountM__olc */ -module loopCountM__olcWcont(do_ins_, do_reD_, inLO, sel_Co_, sel_Ld_, sel_rD_, - sin, flag_D__clr_, flag_D__set_, ilc_load_, sout, mc, p1p, p2p, rd); +module loopCountM__olcWcont(do_ins_, doneLO_M_, inLO, sel_Co_, sel_Ld_, + sel_rD_, sin, flag_D__clr_, flag_D__set_, ilc_load_, sout, mc, p1p, p2p, + rd); input do_ins_; - input do_reD_; + input doneLO_M_; input [1:6] inLO; input sel_Co_; input sel_Ld_; @@ -5809,7 +5789,7 @@ module loopCountM__olcWcont(do_ins_, do_reD_, inLO, sel_Co_, sel_Ld_, sel_rD_, wire [1:6] bitt; wire [1:2] s; - loopCountM__loadORcount loadORco_0(.do_ins_(do_ins_), .do_reD_(do_reD_), + loopCountM__loadORcount loadORco_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_), .mc(mc), .olc_zero_(olc_zero_), .olc_zoo_(olc_zoo_), .sel_Co_(sel_Co_), .sel_Ld_(sel_Ld_), .sel_rD_(sel_rD_), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .ilc_load_(ilc_load_), .olc_dec_(olc_dec_), @@ -5882,7 +5862,7 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] , supply1 vdd; supply0 gnd; - wire do_reD_, flag_B__clr_, flag_B__set_, ilc_load_, net_244, net_249; + wire doneLO_M_, flag_B__clr_, flag_B__set_, ilc_load_, net_244, net_249; wire net_279; wiresL__bitAssignments bitAssig_0(); @@ -5898,7 +5878,7 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] , .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .pred_D_(pred_D_), .pred_T_(pred_T_), .sel_Di_( \ps[18] ), .sel_Mv_( \ps[25] ), .sel_Ti_( \ps[19] ), .sel_Tp_( \ps[26] ), .sin(net_249), .succ_sf_(succ_sf_), - .do_reD_(do_reD_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_), + .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_), .sout(sor[1]), .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5])); loopCountM__muxForD muxForD_0(.in(in[1:6]), .sel( \ps[20] ), .outLO({ \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] , @@ -5915,12 +5895,12 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] , .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), .sin(net_244), .do_ins_(do_ins_), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .sout(net_249), .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5])); - loopCountM__olcWcont olcWcont_0(.do_ins_(do_ins_), .do_reD_(do_reD_), .inLO({ - \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , \inLO[6] }), - .sel_Co_( \ps[24] ), .sel_Ld_( \ps[23] ), .sel_rD_( \ps[21] ), - .sin(net_279), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), - .ilc_load_(ilc_load_), .sout(net_244), .mc(sir[9]), .p1p(sir[3]), - .p2p(sir[2]), .rd(sir[5])); + loopCountM__olcWcont olcWcont_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_), + .inLO({ \inLO[1] , \inLO[2] , \inLO[3] , \inLO[4] , \inLO[5] , + \inLO[6] }), .sel_Co_( \ps[24] ), .sel_Ld_( \ps[23] ), .sel_rD_( \ps[21] + ), .sin(net_279), .flag_D__clr_(flag_D__clr_), + .flag_D__set_(flag_D__set_), .ilc_load_(ilc_load_), .sout(net_244), + .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5])); wiresL__tranCap tc_1_(); wiresL__tranCap tc_2_(); wiresL__tranCap tc_3_(); @@ -5942,7 +5922,7 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] , orangeTSMC090nm__wire90 wire90_9(.a(flag_D__set_)); orangeTSMC090nm__wire90 wire90_10(.a(flag_D__clr_)); orangeTSMC090nm__wire90 wire90_24(.a(ilc_load_)); - orangeTSMC090nm__wire90 wire90_25(.a(do_reD_)); + orangeTSMC090nm__wire90 wire90_25(.a(doneLO_M_)); endmodule /* stagesM__outDockCenter */ module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_, -- 1.7.10.4