From 48ce3256af9af5a24ba84f049d41d6251b038657 Mon Sep 17 00:00:00 2001 From: adam Date: Mon, 10 Nov 2008 12:28:40 +0100 Subject: [PATCH] add Trigger.invert() --- src/edu/berkeley/fleet/fpga/verilog/Verilog.java | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java index 56e8fbb..06e474c 100644 --- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java +++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java @@ -54,6 +54,14 @@ public class Verilog { public static interface Trigger { public String getVerilogTrigger(); + public Trigger invert(); + } + + public static class InvertedTrigger implements Trigger { + private final Trigger original; + public InvertedTrigger(Trigger original) { this.original = original; } + public String getVerilogTrigger() { return "!("+original.getVerilogTrigger()+")"; } + public Trigger invert() { return original; } } public static interface Assignable { @@ -89,6 +97,7 @@ public class Verilog { public String getVerilogTrigger() { return "&& (("+condition+") ? (1 " + trigger.getVerilogTrigger() + ") : 1)"; } + public Trigger invert() { return new InvertedTrigger(this); } } public static class SimpleAssignable implements Assignable { @@ -249,6 +258,7 @@ public class Verilog { public abstract String getDeclaration(); public abstract String getAssignments(); public abstract void connect(SinkPort driven); + public Trigger invert() { return new InvertedTrigger(this); } } public static class InstantiatedModule { -- 1.7.10.4