From 4fd6112c3d8fd5b80d275d9152af4540084952c5 Mon Sep 17 00:00:00 2001
From: adam <adam@megacz.com>
Date: Sun, 27 Jan 2008 14:10:13 +0100
Subject: [PATCH] propagate break signal as reset

---
 src/edu/berkeley/fleet/fpga/main.v |   67 ++++++------------------------------
 1 file changed, 11 insertions(+), 56 deletions(-)

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index 86e0133..cd05049 100644
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -17,8 +17,9 @@ module main
 
   wire clk;
   assign clk = sys_clk_pin;
+  wire break;
   wire rst;
-  assign rst = sys_rst_pin;
+  assign rst = sys_rst_pin || break;
 
   wire       data_to_host_full;
   wire       data_to_host_write_enable;
@@ -32,36 +33,10 @@ module main
   reg re;
   reg [7:0] data_to_host_r;
 
-/*
-  assign data_to_host              = data_to_host_r;
-  assign data_to_host_write_enable = we;
-  assign data_to_fleet_read_enable = re;
-
-  reg [7:0] count;
-  initial count = 0;
-  initial we = 0;
-  initial re = 0;
-  initial data_to_host_r = 107;
-  always @(posedge clk) begin
-    if (re && !data_to_fleet_empty) begin
-      data_to_host_r <= data_to_fleet;
-      we <= 1;
-    end else begin
-      we <= 0;
-    end
-    if (data_to_host_full || data_to_fleet_empty) begin
-      re <= 0;
-    end else begin
-      re <= 1;
-    end
-  end
-*/
-
   wire ser_rst;
   reg ser_rst_r;
   initial ser_rst_r = 0;
   assign ser_rst = rst & ser_rst_r;
-   wire break;
 
   wire sio_ce;
   wire sio_ce_x4;
@@ -93,6 +68,7 @@ module main
    wire root_out_r;
    wire [7:0] root_in_d;
 
+
    root my_root(clk, rst, 
                 root_in_r,  root_in_a,  root_in_d,
                 root_out_r, root_out_a, data_to_host);
@@ -119,45 +95,24 @@ module main
      end
    end
 
-   // awful hack to flush the superfluous null byte that seems to appear on bootup
-   reg [15:0] boot_counter;
-
    // host -> fpga
    always @(posedge clk)
    begin
      ser_rst_r <= 1;
-/*
-     if (boot_counter != 500) begin
-       data_to_fleet_read_enable_reg = 1;
-       if (sio_ce) begin
-         boot_counter <= boot_counter + 1;
-       end
+     data_to_fleet_read_enable_reg = 0;
+     if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
+        root_in_r_reg = 1;
+        root_in_d_reg = data_to_fleet;
+        data_to_fleet_read_enable_reg = 1;
      end else begin
-*/
-       data_to_fleet_read_enable_reg = 0;
-/*
-       if (break) begin
-          root_in_d_reg = 98;
-          root_in_r_reg = 1;
-       end else
-*/
-       if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
-          root_in_r_reg = 1;
-          root_in_d_reg = data_to_fleet;
-          data_to_fleet_read_enable_reg = 1;
-       end else begin
-          if (root_in_a) begin
-            root_in_r_reg = 0;
-          end
-       end
-/*
+        if (root_in_a) begin
+          root_in_r_reg = 0;
+        end
      end
-*/
    end
 
    initial
    begin
-     boot_counter = 0;
      root_in_r_reg = 0;
      root_in_d_reg = 0;
      root_out_a_reg = 0;
-- 
1.7.10.4