From 55673a7abfb1513b501a96e3ec489eaa72a0b805 Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Mon, 20 Apr 2009 22:26:22 +0000 Subject: [PATCH] add additional masterClear() code for Verilog simulations --- .../com/sun/vlsi/chips/marina/test/Marina.java | 80 ++++++++++++++++---- 1 file changed, 67 insertions(+), 13 deletions(-) diff --git a/testCode/com/sun/vlsi/chips/marina/test/Marina.java b/testCode/com/sun/vlsi/chips/marina/test/Marina.java index 1e772d2..b1d4eaa 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/Marina.java +++ b/testCode/com/sun/vlsi/chips/marina/test/Marina.java @@ -57,12 +57,12 @@ public class Marina { private int value; private Ilc() { shiftReport(true, false); - BitVector odd = cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH_ODD).bitReverse().not(); + BitVector odd = cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH_ODD).bitReverse().not(); BitVector even = cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH_EVEN).bitReverse().not(); - BitVector ret = new BitVector(8, "olc"); + BitVector ret = new BitVector(8, "olc"); for(int i=0; i<4; i++) { - ret.set(i*2, odd.get(i)); - ret.set(i*2+1, even.get(i)); + ret.set(i*2+1, odd.get(i)); + ret.set(i*2, even.get(i)); } value = (int)ret.toLong(); } @@ -82,7 +82,7 @@ public class Marina { } /** Get the 6 bits of count of the inner loop counter */ public int getCount() { - return value & 0x3f; + return value & 0xff; } } @@ -136,14 +136,68 @@ public class Marina { data.clear(); instrIn.clear(); - ((VerilogModel)model).setNodeState("sid[9]", 1); - ((VerilogModel)model).setNodeState("sic[9]", 1); - ((VerilogModel)model).setNodeState("sir[9]", 1); - model.waitNS(WIDTH); - ((VerilogModel)model).setNodeState("sid[9]", 0); - ((VerilogModel)model).setNodeState("sic[9]", 0); - ((VerilogModel)model).setNodeState("sir[9]", 0); - model.waitNS(1); + VerilogModel vm = (VerilogModel)model; + // + // In real life the flags come up with some undefined + // value. In verilog we need to prevent the X'es from + // propagating, so we force the flags to a known value + // + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__set_", 0); + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__clr_", 1); + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__set_", 0); + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__clr_", 1); + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__set_", 0); + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__clr_", 1); + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@0.net_50", 0); // A + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@1.net_50", 0); // B + vm.setNodeState("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_", 0); // C + + // force the OLC to zero + for(int i=1; i<=6; i++) + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.bitt["+i+"]", 1); + + // set the ILC input to 1 + for(int i=1; i<=8; i++) { + if (i!=7) + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.\\inLO["+i+"]", (i==1)?0:1); + } + + // pulse ilc[load] + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 1); + model.waitNS(1000); + vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 0); + model.waitNS(1000); + + vm.setNodeState("sid[9]", 1); + vm.setNodeState("sic[9]", 1); + vm.setNodeState("sir[9]", 1); + model.waitNS(1000); + vm.setNodeState("sid[9]", 0); + vm.setNodeState("sic[9]", 0); + vm.setNodeState("sir[9]", 0); + model.waitNS(1000); + + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__set_"); + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__clr_"); + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__set_"); + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__clr_"); + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__set_"); + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_D__clr_"); + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@0.net_50"); + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@1.net_50"); + + // Every move instruction, even those with Ti=0,Di=0, + // loads the C-flag. It will get loaded with an "X", + // which will then leak into the flags and from there the + // predicate. + //vm.releaseNode("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_"); + + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_"); + for(int i=1; i<=8; i++) { + if (i!=7) + vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.\\inLO["+i+"] "); + } + model.waitNS(1000); // the proper stopper states come up in an undefined ("X") // state, so under Verilog we need to force them to a -- 1.7.10.4