From 56553c511a9c2a6d110095ea7ca7c860fa7a31c5 Mon Sep 17 00:00:00 2001 From: adam Date: Mon, 12 Feb 2007 12:37:18 +0100 Subject: [PATCH] migrate verilog into ship files --- Makefile | 3 + ships/Alu1.ship | 43 +++++++ ships/Alu2.ship | 53 +++++++++ ships/Debug.ship | 19 +++ ships/Dscratch.ship | 87 ++++++++++++++ ships/Execute.ship | 48 ++++++++ ships/Fifo.ship | 25 ++++ ships/Halt.ship | 1 + ships/Iscratch.ship | 171 +++++++++++++++++++++++++++ ships/Lut.ship | 1 + ships/Shift.ship | 1 + src/edu/berkeley/fleet/slipway/Slipway.java | 16 +++ src/edu/berkeley/fleet/slipway/alu1.v | 3 + src/edu/berkeley/fleet/slipway/alu2.v | 4 + src/edu/berkeley/fleet/slipway/dcache.v | 84 ------------- src/edu/berkeley/fleet/slipway/debug.v | 2 + src/edu/berkeley/fleet/slipway/execute.inc | 36 ------ src/edu/berkeley/fleet/slipway/execute.v | 40 ++++++- src/edu/berkeley/fleet/slipway/fifo.v | 2 + src/edu/berkeley/fleet/slipway/icache.v | 169 -------------------------- 20 files changed, 518 insertions(+), 290 deletions(-) delete mode 100644 src/edu/berkeley/fleet/slipway/dcache.v delete mode 100644 src/edu/berkeley/fleet/slipway/execute.inc delete mode 100644 src/edu/berkeley/fleet/slipway/icache.v diff --git a/Makefile b/Makefile index 40883fe..450e739 100644 --- a/Makefile +++ b/Makefile @@ -64,6 +64,9 @@ build/fabric.v: $(verilog_files) src/edu/berkeley/fleet/slipway/Slipway.java build/main.bit: build/fabric.v $(verilog_files) make fleet.jar + for A in `find ships -name \*.ship`;\ + do java -cp build/class edu.berkeley.fleet.Main target=fpga expand $$A;\ + done rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir} ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_xilinx}' scp ${host}:${remote_dir}/build/main.bit build/ diff --git a/ships/Alu1.ship b/ships/Alu1.ship index 10170f7..7f487c2 100644 --- a/ships/Alu1.ship +++ b/ships/Alu1.ship @@ -32,6 +32,49 @@ data out: out == ArchSim ============================================================== == FPGA ============================================================== +`include "macros.v" + +module alu1 (clk, + a_r, a_a_, a_d, + op_r, op_a_, op_d, + out_r_, out_a, out_d_); + + input clk; + `input(a_r, a_a, a_a_, [(`DATAWIDTH-1):0], a_d) + `input(op_r, op_a, op_a_, [(`DATAWIDTH-1):0], op_d) + `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_) + `defreg(out_d_, [(`DATAWIDTH-1):0], out_d) + + reg have_a; + reg [(`DATAWIDTH-1):0] reg_a; + reg have_op; + reg [(`DATAWIDTH-1):0] reg_op; + + always @(posedge clk) begin + if (!have_a) begin + `onread(a_r, a_a) have_a = 1; reg_a = a_d; end + end + if (!have_op) begin + `onread(op_r, op_a) have_op = 1; reg_op = op_d; end + end + + if (have_a && have_op) begin + case (reg_op) + 0: out_d = -reg_a; + 1: out_d = reg_a+1; + 2: out_d = reg_a-1; + 3: out_d = (reg_a<0) ? (-reg_a) : reg_a; + default: out_d = 0; + endcase + `onwrite(out_r, out_a) + have_a = 0; + have_op = 0; + end + end + end + +endmodule + == Contributors ========================================================= Adam Megacz diff --git a/ships/Alu2.ship b/ships/Alu2.ship index 1314407..607a16e 100644 --- a/ships/Alu2.ship +++ b/ships/Alu2.ship @@ -45,6 +45,59 @@ public void service() { == ArchSim ============================================================== == FPGA ============================================================== +`include "macros.v" + +module alu2 (clk, + a_r, a_a_, a_d, + b_r, b_a_, b_d, + op_r, op_a_, op_d, + out_r_, out_a, out_d_); + + input clk; + `input(a_r, a_a, a_a_, [(`DATAWIDTH-1):0], a_d) + `input(b_r, b_a, b_a_, [(`DATAWIDTH-1):0], b_d) + `input(op_r, op_a, op_a_, [(`DATAWIDTH-1):0], op_d) + `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_) + `defreg(out_d_, [(`DATAWIDTH-1):0], out_d) + + reg have_a; + reg [(`DATAWIDTH-1):0] reg_a; + reg have_b; + reg [(`DATAWIDTH-1):0] reg_b; + reg have_op; + reg [(`DATAWIDTH-1):0] reg_op; + + always @(posedge clk) begin + if (!have_a) begin + `onread(a_r, a_a) have_a = 1; reg_a = a_d; end + end + if (!have_b) begin + `onread(b_r, b_a) have_b = 1; reg_b = b_d; end + end + if (!have_op) begin + `onread(op_r, op_a) have_op = 1; reg_op = op_d; end + end + + if (have_a && have_b && have_op) begin + case (reg_op) + 0: out_d = reg_a + reg_b; + 1: out_d = reg_a - reg_b; + //2: out_d = reg_a * reg_b; // will not synthesize --AM + //3: out_d = reg_a / reg_b; // will not synthesize --AM + //4: out_d = reg_a % reg_b; // will not synthesize --AM + default: out_d = 0; + endcase + `onwrite(out_r, out_a) + have_a = 0; + have_b = 0; + have_op = 0; + end + end + end + +endmodule + + == Contributors ========================================================= Adam Megacz diff --git a/ships/Debug.ship b/ships/Debug.ship index 0c3120a..aaeff49 100644 --- a/ships/Debug.ship +++ b/ships/Debug.ship @@ -16,6 +16,25 @@ public void service() { == ArchSim ============================================================== == FPGA ============================================================== +`include "macros.v" + +module debug (clk, data_debug_data_r, data_debug_data_a, data_debug_data, + data_debug_out_r, data_debug_out_a, data_debug_out ); + input clk; + + input data_debug_data_r; + output data_debug_data_a; + input [`DATAWIDTH:0] data_debug_data; + + output data_debug_out_r; + input data_debug_out_a; + output [`DATAWIDTH:0] data_debug_out; + + assign data_debug_out_r = data_debug_data_r; + assign data_debug_data_a = data_debug_out_a; + assign data_debug_out = data_debug_data; + +endmodule == Contributors ========================================================= Adam Megacz diff --git a/ships/Dscratch.ship b/ships/Dscratch.ship index 9b05a11..08c4413 100644 --- a/ships/Dscratch.ship +++ b/ships/Dscratch.ship @@ -36,7 +36,94 @@ token out: write_done } == ArchSim ============================================================== + == FPGA ============================================================== +`include "macros.v" +`define BRAM_ADDR_WIDTH 14 +`define BRAM_DATA_WIDTH `DATAWIDTH +`define BRAM_NAME dscratch_bram +`include "bram.inc" + +module dscratch (clk, + read_addr_r, read_addr_a_, read_addr_d, + read_data_r_, read_data_a, read_data_d_, + write_addr_r, write_addr_a_, write_addr_d, + write_data_r, write_data_a_, write_data_d, + write_done_r_, write_done_a, write_done_d_ + ); + + input clk; + `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d) + `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_) + `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d) + + `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d) + `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d) + `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_) + `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d) + + reg bram_we; + wire bram_we_; + assign bram_we_ = bram_we; + wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data; + reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address; + wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address; + reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data; + wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_; + assign bram_write_data_ = bram_write_data; + `BRAM_NAME mybram(clk, + bram_we_, bram_write_address, + bram_read_address, bram_write_data_, + not_connected, bram_read_data); + + reg send_done; + + reg have_read; initial have_read = 0; + reg read_pending; initial read_pending = 0; + assign bram_read_address = read_addr_d; + + always @(posedge clk) begin + bram_we = 0; + if (send_done) begin + `onwrite(write_done_r, write_done_a) + send_done = 0; + end + end else begin + if (!write_addr_r && write_addr_a) write_addr_a = 0; + if (!write_data_r && write_data_a) write_data_a = 0; + if (write_addr_r && write_data_r) begin + write_addr_a = 1; + write_data_a = 1; + bram_we = 1; + send_done = 1; + bram_write_address = write_addr_d; + bram_write_data = write_data_d; + end + end + + if (read_pending) begin + read_pending <= 0; + have_read <= 1; + read_data_d <= bram_read_data; + end else if (have_read) begin + `onwrite(read_data_r, read_data_a) + have_read <= 0; + end + end else begin + `onread(read_addr_r, read_addr_a) + // ======= Careful with the timing here! ===================== + // We MUST capture bram_read_data on the very next clock since + // read_addr_d is free to change after the next clock + // =========================================================== + read_pending <= 1; + end + end + + end + +endmodule + + == Constants ======================================================== == TeX ============================================================== diff --git a/ships/Execute.ship b/ships/Execute.ship index 0946121..a50b463 100644 --- a/ships/Execute.ship +++ b/ships/Execute.ship @@ -12,6 +12,54 @@ data in: in == ArchSim ============================================================== == FPGA ============================================================== +`include "macros.v" + +module execute (clk, command_r, command_a_, command_d, + ihorn_r_, ihorn_a, ihorn_d_, + dhorn_r_, dhorn_a, dhorn_d_ + ); + input clk; + + `input(command_r, command_a, command_a_, [(`DATAWIDTH-1):0], command_d) + `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_) + `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d) + `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_) + `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d) + + reg ihorn_full; + reg dhorn_full; + + always @(posedge clk) begin + if (ihorn_full) begin + `onwrite(ihorn_r, ihorn_a) + ihorn_full = 0; + end + end else if (dhorn_full) begin + `onwrite(dhorn_r, dhorn_a) + dhorn_full = 0; + end + end else begin + `onread(command_r, command_a) + case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)]) + 0: begin + ihorn_full = 1; + ihorn_d = command_d; + end + //01: + 2: begin + dhorn_full = 1; + `packet_data(dhorn_d) = command_d[23:0]; + `packet_dest(dhorn_d) = command_d[34:24]; + end + //11: + endcase + end + end + end + + +endmodule + == Contributors ========================================================= Adam Megacz diff --git a/ships/Fifo.ship b/ships/Fifo.ship index 8c96494..f4d8ea1 100644 --- a/ships/Fifo.ship +++ b/ships/Fifo.ship @@ -19,6 +19,31 @@ data out: out == ArchSim ============================================================== == FPGA ============================================================== +`include "macros.v" + +// fifo *ship*: a 16-deep word-wide fifo +module fifo (clk, + in_r, in_a, in_d, + out_r, out_a, out_d); + + input clk; + input in_r; + input out_a; + output in_a; + output out_r; + input [(`DATAWIDTH-1):0] in_d; + output [(`DATAWIDTH-1):0] out_d; + + wire [(`DATAWIDTH-1):0] d12; + wire [(`DATAWIDTH-1):0] d23; + wire [(`DATAWIDTH-1):0] d34; + + fifo4 s1(clk, in_r, in_a, in_d, r12, a12, d12); + fifo4 s2(clk, r12, a12, d12, r23, a23, d23); + fifo4 s3(clk, r23, a23, d23, r34, a34, d34); + fifo4 s4(clk, r34, a34, d34, out_r, out_a, out_d); + +endmodule == Contributors ========================================================= Adam Megacz diff --git a/ships/Halt.ship b/ships/Halt.ship index 49c2ce4..5e0c9df 100644 --- a/ships/Halt.ship +++ b/ships/Halt.ship @@ -18,6 +18,7 @@ public void service() { == ArchSim ============================================================== == FPGA ============================================================== +// not implemented FIXME == Contributors ========================================================= Adam Megacz diff --git a/ships/Iscratch.ship b/ships/Iscratch.ship index a09290c..bc502cb 100644 --- a/ships/Iscratch.ship +++ b/ships/Iscratch.ship @@ -69,6 +69,177 @@ data in: cbd == TeX ============================================================== == ArchSim ============================================================== == FPGA ============================================================== +`include "macros.v" +`define BRAM_ADDR_WIDTH 14 +`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH +`define BRAM_NAME iscratch_bram +`include "bram.inc" + +module iscratch (clk, + write_addr_r, write_addr_a_, write_addr_d, + write_data_r, write_data_a_, write_data_d, + write_done_r_, write_done_a, write_done_d_, + cbd_r, cbd_a_, cbd_d, + preload_r, preload_a_, preload_d, + ihorn_r_, ihorn_a, ihorn_d_, + dhorn_r_, dhorn_a, dhorn_d_ + ); + + input clk; + `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d) + `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d) + `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_) + `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d) + + `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d) + `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d) + `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_) + `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d) + `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_) + `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d) + + reg ihorn_full; + initial ihorn_full = 0; + reg dhorn_full; + initial dhorn_full = 0; + reg command_valid; + initial command_valid = 0; + + reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos; + reg [(`BRAM_ADDR_WIDTH-1):0] preload_size; + initial preload_size = 0; + + reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from; + reg [(`BRAM_ADDR_WIDTH-1):0] temp_base; + reg [(`CODEBAG_SIZE_BITS-1):0] temp_size; + reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base; + reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size; + reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos; + reg [(`INSTRUCTION_WIDTH-1):0] command; + reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0]; + reg send_done; + + reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp; + reg [(`DATAWIDTH-1):0] data; + + reg write_flag; + reg [(`BRAM_ADDR_WIDTH-1):0] write_addr; + reg [(`BRAM_DATA_WIDTH-1):0] write_data; + + wire [(`BRAM_DATA_WIDTH-1):0] ramread; + + reg command_valid_read; + initial command_valid_read = 0; + + reg launched; + initial launched = 0; + + iscratch_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread); + + always @(posedge clk) begin + + write_flag <= 0; + + if (!write_addr_r && write_addr_a) write_addr_a = 0; + if (!write_data_r && write_data_a) write_data_a = 0; + + if (command_valid_read) begin + command_valid_read <= 0; + command_valid <= 1; + + end else if (send_done) begin + `onwrite(write_done_r, write_done_a) + send_done <= 0; + end + + end else if (write_addr_r && write_data_r) begin + write_addr_a = 1; + write_data_a = 1; + send_done <= 1; + write_flag <= 1; + write_addr <= write_addr_d; + write_data <= write_data_d; + + end else if (ihorn_full && launched) begin + `onwrite(ihorn_r, ihorn_a) + ihorn_full <= 0; + end + + end else if (dhorn_full) begin + `onwrite(dhorn_r, dhorn_a) + dhorn_full <= 0; + end + + end else if (command_valid) begin + command_valid <= 0; + command = ramread; + case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)]) + 0: begin + ihorn_full <= 1; + ihorn_d <= command; + end + 1: begin + dhorn_full <= 1; + temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0]; + temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} }); + data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp; + data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0]; + `packet_data(dhorn_d) <= temp; + `packet_dest(dhorn_d) <= + command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)]; + end + 2: begin + dhorn_full <= 1; + `packet_data(dhorn_d) <= command[23:0]; + `packet_dest(dhorn_d) <= command[34:24]; + end + 3: begin + dhorn_full <= 1; + `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from; + `packet_dest(dhorn_d) <= command[34:24]; + end + endcase + + end else if (cbd_pos < cbd_size) begin + current_instruction_read_from <= cbd_base+cbd_pos; + command_valid_read <= 1; + cbd_pos <= cbd_pos + 1; + + end else begin + `onread(cbd_r, cbd_a) + cbd_pos <= 0; + cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0]; + cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)]; + + end else begin + `onread(preload_r, preload_a) + if (preload_size == 0) begin + preload_size <= preload_d; + end else if (!launched) begin + write_flag <= 1; + write_data <= preload_d; + write_addr <= preload_pos; + if (preload_pos == 0) begin + temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)]; + temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0]; + end + if ((preload_pos+1) == preload_size) begin + cbd_pos <= 0; + cbd_base <= temp_base; + cbd_size <= temp_size; + launched <= 1; + end + preload_pos <= preload_pos + 1; + end + end + end + end + end +endmodule + + + + == Contributors ========================================================= Adam Megacz diff --git a/ships/Lut.ship b/ships/Lut.ship index e920c9d..2f18657 100644 --- a/ships/Lut.ship +++ b/ships/Lut.ship @@ -26,6 +26,7 @@ data out: out == ArchSim ============================================================== == FPGA ============================================================== +// not implemented FIXME == Contributors ========================================================= Adam Megacz diff --git a/ships/Shift.ship b/ships/Shift.ship index 8450c78..dfba5e1 100644 --- a/ships/Shift.ship +++ b/ships/Shift.ship @@ -20,6 +20,7 @@ data out: out == ArchSim ============================================================== == FPGA ============================================================== +// not implemented FIXME! == Contributors ========================================================= Adam Megacz diff --git a/src/edu/berkeley/fleet/slipway/Slipway.java b/src/edu/berkeley/fleet/slipway/Slipway.java index b6d96f1..a73fd0f 100644 --- a/src/edu/berkeley/fleet/slipway/Slipway.java +++ b/src/edu/berkeley/fleet/slipway/Slipway.java @@ -1,5 +1,6 @@ package edu.berkeley.fleet.slipway; import edu.berkeley.fleet.interpreter.*; +import edu.berkeley.fleet.doc.*; import edu.berkeley.fleet.api.*; import edu.berkeley.fleet.ies44.*; import edu.berkeley.fleet.*; @@ -302,4 +303,19 @@ public class Slipway extends Interpreter { return ship.getType() + ship.getOrdinal(); } + public void expand(ShipDescription sd) { + try { + String filename = sd.name.toLowerCase(); + File outf = new File("src/edu/berkeley/fleet/slipway/"+filename+".v"); + new File(outf.getParent()).mkdirs(); + System.err.println("writing to " + outf); + FileOutputStream out = new FileOutputStream(outf); + PrintWriter pw = new PrintWriter(out); + + pw.println(sd.sections.get("fpga")); + pw.flush(); + pw.close(); + } catch (Exception e) { throw new RuntimeException(e); } + } + } \ No newline at end of file diff --git a/src/edu/berkeley/fleet/slipway/alu1.v b/src/edu/berkeley/fleet/slipway/alu1.v index 89659be..ac813d0 100644 --- a/src/edu/berkeley/fleet/slipway/alu1.v +++ b/src/edu/berkeley/fleet/slipway/alu1.v @@ -40,3 +40,6 @@ module alu1 (clk, end endmodule + + + diff --git a/src/edu/berkeley/fleet/slipway/alu2.v b/src/edu/berkeley/fleet/slipway/alu2.v index 76acea5..57b11d2 100644 --- a/src/edu/berkeley/fleet/slipway/alu2.v +++ b/src/edu/berkeley/fleet/slipway/alu2.v @@ -49,3 +49,7 @@ module alu2 (clk, end endmodule + + + + diff --git a/src/edu/berkeley/fleet/slipway/dcache.v b/src/edu/berkeley/fleet/slipway/dcache.v deleted file mode 100644 index ccea08b..0000000 --- a/src/edu/berkeley/fleet/slipway/dcache.v +++ /dev/null @@ -1,84 +0,0 @@ -`include "macros.v" -`define BRAM_ADDR_WIDTH 14 -`define BRAM_DATA_WIDTH `DATAWIDTH -`define BRAM_NAME dcache_bram -`include "bram.inc" - -module dcache (clk, - read_addr_r, read_addr_a_, read_addr_d, - read_data_r_, read_data_a, read_data_d_, - write_addr_r, write_addr_a_, write_addr_d, - write_data_r, write_data_a_, write_data_d, - write_done_r_, write_done_a, write_done_d_ - ); - - input clk; - `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d) - `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_) - `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d) - - `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d) - `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d) - `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_) - `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d) - - reg bram_we; - wire bram_we_; - assign bram_we_ = bram_we; - wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data; - reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address; - wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address; - reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data; - wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_; - assign bram_write_data_ = bram_write_data; - `BRAM_NAME mybram(clk, - bram_we_, bram_write_address, - bram_read_address, bram_write_data_, - not_connected, bram_read_data); - - reg send_done; - - reg have_read; initial have_read = 0; - reg read_pending; initial read_pending = 0; - assign bram_read_address = read_addr_d; - - always @(posedge clk) begin - bram_we = 0; - if (send_done) begin - `onwrite(write_done_r, write_done_a) - send_done = 0; - end - end else begin - if (!write_addr_r && write_addr_a) write_addr_a = 0; - if (!write_data_r && write_data_a) write_data_a = 0; - if (write_addr_r && write_data_r) begin - write_addr_a = 1; - write_data_a = 1; - bram_we = 1; - send_done = 1; - bram_write_address = write_addr_d; - bram_write_data = write_data_d; - end - end - - if (read_pending) begin - read_pending <= 0; - have_read <= 1; - read_data_d <= bram_read_data; - end else if (have_read) begin - `onwrite(read_data_r, read_data_a) - have_read <= 0; - end - end else begin - `onread(read_addr_r, read_addr_a) - // ======= Careful with the timing here! ===================== - // We MUST capture bram_read_data on the very next clock since - // read_addr_d is free to change after the next clock - // =========================================================== - read_pending <= 1; - end - end - - end - -endmodule diff --git a/src/edu/berkeley/fleet/slipway/debug.v b/src/edu/berkeley/fleet/slipway/debug.v index 6e64c10..30a6474 100644 --- a/src/edu/berkeley/fleet/slipway/debug.v +++ b/src/edu/berkeley/fleet/slipway/debug.v @@ -17,3 +17,5 @@ module debug (clk, data_debug_data_r, data_debug_data_a, data_debug_data, assign data_debug_out = data_debug_data; endmodule + + diff --git a/src/edu/berkeley/fleet/slipway/execute.inc b/src/edu/berkeley/fleet/slipway/execute.inc deleted file mode 100644 index 94ceb11..0000000 --- a/src/edu/berkeley/fleet/slipway/execute.inc +++ /dev/null @@ -1,36 +0,0 @@ - `input(command_r, command_a, command_a_, [(`DATAWIDTH-1):0], command_d) - `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_) - `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d) - `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_) - `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d) - - reg ihorn_full; - reg dhorn_full; - - always @(posedge clk) begin - if (ihorn_full) begin - `onwrite(ihorn_r, ihorn_a) - ihorn_full = 0; - end - end else if (dhorn_full) begin - `onwrite(dhorn_r, dhorn_a) - dhorn_full = 0; - end - end else begin - `onread(command_r, command_a) - case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)]) - 0: begin - ihorn_full = 1; - ihorn_d = command_d; - end - //01: - 2: begin - dhorn_full = 1; - `packet_data(dhorn_d) = command_d[23:0]; - `packet_dest(dhorn_d) = command_d[34:24]; - end - //11: - endcase - end - end - end diff --git a/src/edu/berkeley/fleet/slipway/execute.v b/src/edu/berkeley/fleet/slipway/execute.v index 623f3af..d8486dc 100644 --- a/src/edu/berkeley/fleet/slipway/execute.v +++ b/src/edu/berkeley/fleet/slipway/execute.v @@ -6,7 +6,45 @@ module execute (clk, command_r, command_a_, command_d, ); input clk; - `include "execute.inc" + `input(command_r, command_a, command_a_, [(`DATAWIDTH-1):0], command_d) + `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_) + `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d) + `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_) + `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d) + + reg ihorn_full; + reg dhorn_full; + + always @(posedge clk) begin + if (ihorn_full) begin + `onwrite(ihorn_r, ihorn_a) + ihorn_full = 0; + end + end else if (dhorn_full) begin + `onwrite(dhorn_r, dhorn_a) + dhorn_full = 0; + end + end else begin + `onread(command_r, command_a) + case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)]) + 0: begin + ihorn_full = 1; + ihorn_d = command_d; + end + //01: + 2: begin + dhorn_full = 1; + `packet_data(dhorn_d) = command_d[23:0]; + `packet_dest(dhorn_d) = command_d[34:24]; + end + //11: + endcase + end + end + end + endmodule + + diff --git a/src/edu/berkeley/fleet/slipway/fifo.v b/src/edu/berkeley/fleet/slipway/fifo.v index 235349c..6bff619 100644 --- a/src/edu/berkeley/fleet/slipway/fifo.v +++ b/src/edu/berkeley/fleet/slipway/fifo.v @@ -23,3 +23,5 @@ module fifo (clk, fifo4 s4(clk, r34, a34, d34, out_r, out_a, out_d); endmodule + + diff --git a/src/edu/berkeley/fleet/slipway/icache.v b/src/edu/berkeley/fleet/slipway/icache.v deleted file mode 100644 index 280ded8..0000000 --- a/src/edu/berkeley/fleet/slipway/icache.v +++ /dev/null @@ -1,169 +0,0 @@ -`include "macros.v" -`define BRAM_ADDR_WIDTH 14 -`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH -`define BRAM_NAME icache_bram -`include "bram.inc" - -module icache (clk, - write_addr_r, write_addr_a_, write_addr_d, - write_data_r, write_data_a_, write_data_d, - write_done_r_, write_done_a, write_done_d_, - cbd_r, cbd_a_, cbd_d, - preload_r, preload_a_, preload_d, - ihorn_r_, ihorn_a, ihorn_d_, - dhorn_r_, dhorn_a, dhorn_d_ - ); - - input clk; - `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d) - `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d) - `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_) - `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d) - - `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d) - `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d) - `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_) - `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d) - `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_) - `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d) - - reg ihorn_full; - initial ihorn_full = 0; - reg dhorn_full; - initial dhorn_full = 0; - reg command_valid; - initial command_valid = 0; - - reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos; - reg [(`BRAM_ADDR_WIDTH-1):0] preload_size; - initial preload_size = 0; - - reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from; - reg [(`BRAM_ADDR_WIDTH-1):0] temp_base; - reg [(`CODEBAG_SIZE_BITS-1):0] temp_size; - reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base; - reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size; - reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos; - reg [(`INSTRUCTION_WIDTH-1):0] command; - reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0]; - reg send_done; - - reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp; - reg [(`DATAWIDTH-1):0] data; - - reg write_flag; - reg [(`BRAM_ADDR_WIDTH-1):0] write_addr; - reg [(`BRAM_DATA_WIDTH-1):0] write_data; - - wire [(`BRAM_DATA_WIDTH-1):0] ramread; - - reg command_valid_read; - initial command_valid_read = 0; - - reg launched; - initial launched = 0; - - icache_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread); - - always @(posedge clk) begin - - write_flag <= 0; - - if (!write_addr_r && write_addr_a) write_addr_a = 0; - if (!write_data_r && write_data_a) write_data_a = 0; - - if (command_valid_read) begin - command_valid_read <= 0; - command_valid <= 1; - - end else if (send_done) begin - `onwrite(write_done_r, write_done_a) - send_done <= 0; - end - - end else if (write_addr_r && write_data_r) begin - write_addr_a = 1; - write_data_a = 1; - send_done <= 1; - write_flag <= 1; - write_addr <= write_addr_d; - write_data <= write_data_d; - - end else if (ihorn_full && launched) begin - `onwrite(ihorn_r, ihorn_a) - ihorn_full <= 0; - end - - end else if (dhorn_full) begin - `onwrite(dhorn_r, dhorn_a) - dhorn_full <= 0; - end - - end else if (command_valid) begin - command_valid <= 0; - command = ramread; - case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)]) - 0: begin - ihorn_full <= 1; - ihorn_d <= command; - end - 1: begin - dhorn_full <= 1; - temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0]; - temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} }); - data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp; - data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0]; - `packet_data(dhorn_d) <= temp; - `packet_dest(dhorn_d) <= - command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)]; - end - 2: begin - dhorn_full <= 1; - `packet_data(dhorn_d) <= command[23:0]; - `packet_dest(dhorn_d) <= command[34:24]; - end - 3: begin - dhorn_full <= 1; - `packet_data(dhorn_d) <= command[23:0] + current_instruction_read_from; - `packet_dest(dhorn_d) <= command[34:24]; - end - endcase - - end else if (cbd_pos < cbd_size) begin - current_instruction_read_from <= cbd_base+cbd_pos; - command_valid_read <= 1; - cbd_pos <= cbd_pos + 1; - - end else begin - `onread(cbd_r, cbd_a) - cbd_pos <= 0; - cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0]; - cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)]; - - end else begin - `onread(preload_r, preload_a) - if (preload_size == 0) begin - preload_size <= preload_d; - end else if (!launched) begin - write_flag <= 1; - write_data <= preload_d; - write_addr <= preload_pos; - if (preload_pos == 0) begin - temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)]; - temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0]; - end - if ((preload_pos+1) == preload_size) begin - cbd_pos <= 0; - cbd_base <= temp_base; - cbd_size <= temp_size; - launched <= 1; - end - preload_pos <= preload_pos + 1; - end - end - end - end - end -endmodule - - -- 1.7.10.4