From 5cc6545c8890979e9b9da487655295deb67e45e0 Mon Sep 17 00:00:00 2001 From: adam Date: Sun, 27 Jan 2008 13:48:09 +0100 Subject: [PATCH] add support for RS-232 break signal --- src/edu/berkeley/fleet/fpga/main.v | 12 ++++++++++-- src/edu/berkeley/fleet/fpga/sasc_top.v | 10 ++++++++-- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v index 505d6a7..86e0133 100644 --- a/src/edu/berkeley/fleet/fpga/main.v +++ b/src/edu/berkeley/fleet/fpga/main.v @@ -61,6 +61,7 @@ module main reg ser_rst_r; initial ser_rst_r = 0; assign ser_rst = rst & ser_rst_r; + wire break; wire sio_ce; wire sio_ce_x4; @@ -77,7 +78,8 @@ module main data_to_fleet_read_enable, data_to_host_write_enable, data_to_host_full, - data_to_fleet_empty); + data_to_fleet_empty, + break); reg data_to_host_write_enable_reg; reg data_to_fleet_read_enable_reg; @@ -95,7 +97,7 @@ module main root_in_r, root_in_a, root_in_d, root_out_r, root_out_a, data_to_host); /* - fifo4 my_root(clk, + fifo4 my_root(clk, rst, root_in_r, root_in_a, root_in_d, root_out_r, root_out_a, data_to_host); */ @@ -133,6 +135,12 @@ module main end else begin */ data_to_fleet_read_enable_reg = 0; +/* + if (break) begin + root_in_d_reg = 98; + root_in_r_reg = 1; + end else +*/ if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin root_in_r_reg = 1; root_in_d_reg = data_to_fleet; diff --git a/src/edu/berkeley/fleet/fpga/sasc_top.v b/src/edu/berkeley/fleet/fpga/sasc_top.v index 5fb2b52..1ebb15a 100644 --- a/src/edu/berkeley/fleet/fpga/sasc_top.v +++ b/src/edu/berkeley/fleet/fpga/sasc_top.v @@ -89,7 +89,8 @@ module sasc_top( clk, rst, sio_ce, sio_ce_x4, // Internal Interface - din_i, dout_o, re_i, we_i, full_o, empty_o); + din_i, dout_o, re_i, we_i, full_o, empty_o, + break_o); input clk; input rst; @@ -97,6 +98,8 @@ input rxd_i; output txd_o; input cts_i; output rts_o; +output break_o; +reg break_r; input sio_ce; input sio_ce_x4; input [7:0] din_i; @@ -237,8 +240,11 @@ always @(posedge clk) always @(posedge clk) rx_go <= #1 (rx_bit_cnt != 4'ha); +assign break_o = break_r; always @(posedge clk) - rx_valid <= #1 (rx_bit_cnt == 4'h9); + rx_valid <= #1 (rx_bit_cnt == 4'h9) && (rxd_s == STOP_BIT); +always @(posedge clk) + break_r <= #1 (rx_bit_cnt == 4'h9) && (rxr[9:1]==8'b0) && (rxd_s == START_BIT); always @(posedge clk) rx_valid_r <= #1 rx_valid; -- 1.7.10.4