From 5d3a1ab879273cf298cddc89c4fce4050ad2083a Mon Sep 17 00:00:00 2001 From: adam Date: Mon, 10 Nov 2008 06:51:27 +0100 Subject: [PATCH] remove timescale.v, bram14.v, vram.v --- src/edu/berkeley/fleet/fpga/Fpga.java | 21 +++++++++++++++++++++ src/edu/berkeley/fleet/fpga/bram14.v | 6 ------ src/edu/berkeley/fleet/fpga/timescale.v | 1 - src/edu/berkeley/fleet/fpga/vram.v | 6 ------ 4 files changed, 21 insertions(+), 13 deletions(-) delete mode 100644 src/edu/berkeley/fleet/fpga/bram14.v delete mode 100644 src/edu/berkeley/fleet/fpga/timescale.v delete mode 100644 src/edu/berkeley/fleet/fpga/vram.v diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java index 9dddcf2..6b1a304 100644 --- a/src/edu/berkeley/fleet/fpga/Fpga.java +++ b/src/edu/berkeley/fleet/fpga/Fpga.java @@ -43,6 +43,27 @@ public class Fpga extends FleetTwoFleet { public static void main(String[] s) throws Exception { new Fpga(new Module("root")).top.dump(s[0]); + PrintWriter pw; + + pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v"))); + pw.println("`timescale 1ns / 10ps"); + pw.close(); + + pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v"))); + pw.println("`define BRAM_ADDR_WIDTH 14"); + pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH"); + pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))"); + pw.println("`define BRAM_NAME bram14"); + pw.println("`include \"bram.inc\""); + pw.close(); + + pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v"))); + pw.println("`define BRAM_ADDR_WIDTH 19"); + pw.println("`define BRAM_DATA_WIDTH 3"); + pw.println("`define BRAM_SIZE (640*480)"); + pw.println("`define BRAM_NAME vram"); + pw.println("`include \"bram.inc\""); + pw.close(); } public Module getVerilogModule() { return top; } diff --git a/src/edu/berkeley/fleet/fpga/bram14.v b/src/edu/berkeley/fleet/fpga/bram14.v deleted file mode 100644 index cb1496f..0000000 --- a/src/edu/berkeley/fleet/fpga/bram14.v +++ /dev/null @@ -1,6 +0,0 @@ -`define BRAM_ADDR_WIDTH 14 -`define BRAM_DATA_WIDTH `DATAWIDTH -`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH)) -`define BRAM_NAME bram14 - -`include "bram.inc" diff --git a/src/edu/berkeley/fleet/fpga/timescale.v b/src/edu/berkeley/fleet/fpga/timescale.v deleted file mode 100644 index ff9e265..0000000 --- a/src/edu/berkeley/fleet/fpga/timescale.v +++ /dev/null @@ -1 +0,0 @@ -`timescale 1ns / 10ps diff --git a/src/edu/berkeley/fleet/fpga/vram.v b/src/edu/berkeley/fleet/fpga/vram.v deleted file mode 100644 index 1aca82f..0000000 --- a/src/edu/berkeley/fleet/fpga/vram.v +++ /dev/null @@ -1,6 +0,0 @@ -`define BRAM_ADDR_WIDTH 19 -`define BRAM_DATA_WIDTH 3 -`define BRAM_SIZE (640*480) -`define BRAM_NAME vram - -`include "bram.inc" -- 1.7.10.4