From 68a850be6819c9d1344acd634f7f5e15750ddd33 Mon Sep 17 00:00:00 2001 From: adam Date: Sat, 12 Apr 2008 13:59:08 +0100 Subject: [PATCH] add commented-out code to send an "ok" after break on rs232 --- src/edu/berkeley/fleet/fpga/Server.java | 12 ++++++++++++ src/edu/berkeley/fleet/fpga/main.v | 19 +++++++++++++++---- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/src/edu/berkeley/fleet/fpga/Server.java b/src/edu/berkeley/fleet/fpga/Server.java index fba1d4c..15aaa1b 100644 --- a/src/edu/berkeley/fleet/fpga/Server.java +++ b/src/edu/berkeley/fleet/fpga/Server.java @@ -130,6 +130,18 @@ public class Server { } }.start(); + /* + int last = 0; + for(int j=0; j<3; j++) + while(true) { + int i = fis.read(); + if (i==-1) return; + System.out.println("leader byte: 0x" + Integer.toString(i, 16) + " '"+((char)i)+"'"); + if (((char)last) == 'o' && ((char)i) == 'k') break; + last = i; + } + */ + System.err.println("reading back..."); while(true) { long result = 0; diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v index 05b66ee..ead2c40 100644 --- a/src/edu/berkeley/fleet/fpga/main.v +++ b/src/edu/berkeley/fleet/fpga/main.v @@ -20,6 +20,7 @@ module main wire break_o; wire break; reg break_last; + reg send_k; initial send_k = 0; wire rst; assign rst = sys_rst_pin; @@ -60,8 +61,10 @@ module main break_o, break); + // break and break_o are _active high_ always @(posedge clk) break_last <= break_o; - assign break = break_o && !break_last; + assign break = break_o && !break_last; + assign break_done = !break_o && break_last; reg data_to_host_write_enable_reg; reg data_to_fleet_read_enable_reg; @@ -97,9 +100,17 @@ module main data_to_host_write_enable_reg = 0; /* if (break) begin - data_to_host_write_enable_reg = 1; - data_to_host_r <= 98; - end else + root_out_a_reg = 0; + data_to_host_write_enable_reg <= 0; +/* + end else if (break_done) begin + data_to_host_write_enable_reg <= 1; + data_to_host_r <= 111; + send_k <= 1; + end else if (send_k) begin + data_to_host_write_enable_reg <= 1; + data_to_host_r <= 107; + send_k <= 0; */ if (root_out_r && !root_out_a_reg && !data_to_host_full) begin data_to_host_write_enable_reg = 1; -- 1.7.10.4