From 691f388b3da0577165b56c23285b4219227f1647 Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Fri, 24 Apr 2009 01:14:08 +0000 Subject: [PATCH] all tests pass except requeue stage tests --- .../com/sun/vlsi/chips/marina/test/Marina.java | 14 +- .../com/sun/vlsi/chips/marina/test/MarinaTest.java | 188 ++++++++++++-------- 2 files changed, 128 insertions(+), 74 deletions(-) diff --git a/testCode/com/sun/vlsi/chips/marina/test/Marina.java b/testCode/com/sun/vlsi/chips/marina/test/Marina.java index 06f8876..d804351 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/Marina.java +++ b/testCode/com/sun/vlsi/chips/marina/test/Marina.java @@ -14,6 +14,9 @@ import edu.berkeley.fleet.api.Instruction; * my test infrastructure. */ public class Marina { + public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE = 5; + public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO = 13; + public static final String DATA_CHAIN = "marina.marina_data"; public static final String CONTROL_CHAIN = "marina.marina_control"; public static final String REPORT_CHAIN = "marina.marina_report"; @@ -146,6 +149,10 @@ public class Marina { vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.aFlag@1.net_50", 0); // B vm.setNodeState("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_", 0); // C + // possible C-flag inputs + vm.setNodeState("southFif@1.tapPropS@1.tapStage@2.addr1in6@0.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE+1)+"]", 0); + vm.setNodeState("southFif@1.tapPropS@1.tapStage@2.addr1in6@0.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO+1)+"]", 0); + // force the OLC to zero for(int i=1; i<=6; i++) vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.inLO["+i+"]", (i==1)?0:1); @@ -159,9 +166,11 @@ public class Marina { // pulse ilc[load] and olc[load] vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 1); vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 1); + vm.setNodeState("southFif@1.tapPropS@1.tapStage@2.addr1in6@0.fire", 1); model.waitNS(1000); vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 0); vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 0); + vm.setNodeState("southFif@1.tapPropS@1.tapStage@2.addr1in6@0.fire", 0); model.waitNS(1000); vm.setNodeState("sid[9]", 1); @@ -186,7 +195,10 @@ public class Marina { // loads the C-flag. It will get loaded with an "X", // which will then leak into the flags and from there the // predicate. - //vm.releaseNode("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_"); + vm.releaseNode("outputDo@0.outM1Pre@0.litDandP@0.latch2in@0.hi2inLat@0.latchKee@0.out_B_"); + vm.releaseNode("southFif@1.tapPropS@1.tapStage@2.addr1in6@0.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE+1)+"]"); + vm.releaseNode("southFif@1.tapPropS@1.tapStage@2.addr1in6@0.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO+1)+"]"); + vm.releaseNode("southFif@1.tapPropS@1.tapStage@2.addr1in6@0.fire"); vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_"); for(int i=1; i<=8; i++) { diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java index caad19f..312624e 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java +++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java @@ -46,9 +46,7 @@ public class MarinaTest { public static final int INSTR_SZ = 36; - public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ONE = 13; - public static final int INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO = 0; - + public static final Instruction.Set.FlagFunction CLEAR_FLAG = Instruction.Set.FlagFunction.ZERO; public static final Instruction.Set.FlagFunction SET_FLAG @@ -247,7 +245,7 @@ public class MarinaTest { if (model instanceof VerilogModel) { VerilogModel vm = (VerilogModel)model; - vm.start("verilog", "marina.v", VerilogModel.DUMPVARS); + vm.start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift); vm.setNodeState("sid[9]", 1); vm.setNodeState("sic[9]", 1); vm.setNodeState("sir[9]", 1); @@ -622,18 +620,18 @@ public class MarinaTest { prln("Inserting ["+(predicate_olc_nonzero?"olc!=0":"olc==0")+"] send data"); marina.instrIn.fill(new Instruction.Move(dock, - predicate_olc_nonzero /* predicate */ + predicate_olc_nonzero // predicate ? only_if_olc_nonzero : only_if_olc_zero , - false, /* torpedoable */ - null, /* path */ - false, /* tokenIn */ - false, /* dataIn */ - false, /* latchData */ - false, /* latchPath */ - true, /* dataOut */ - false /* tokenOut */ + false, // torpedoable + null, // path + false, // tokenIn + false, // dataIn + false, // latchData + false, // latchPath + true, // dataOut + false // tokenOut )); toks = marina.data.drainMany(); int expected = (predicate_olc_nonzero == (olc!=0)) ? 1 : 0; @@ -1191,7 +1189,7 @@ public class MarinaTest { BitVector addr = new BitVector(14, "empty"); for(int i=0; i dataItems; for(boolean torpedoable : new boolean[] { true, false }) { + + prln("send token"); + marina.instrIn.fill(new Instruction.Move(dock, + Predicate.IgnoreFlagD, // predicate + false, // torpedoable + null, // path + false, // tokenIn + false, // dataIn + false, // latchData + false, // latchPath + false, // dataOut + true // tokenOut + )); + prln("set ilc=\\infty"); marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter,SetSource.Infinity)); - - prln("nop"); + + prln("recv-and-send token"); marina.instrIn.fill(new Instruction.Move(dock, - Predicate.IgnoreFlagD, /* predicate */ - torpedoable, /* torpedoable */ - null, /* path */ - false, /* tokenIn */ - false, /* dataIn */ - false, /* latchData */ - false, /* latchPath */ - false, /* dataOut */ - false /* tokenOut */ + Predicate.IgnoreFlagD, // predicate + torpedoable, // torpedoable + null, // path + true, // tokenIn + false, // dataIn + false, // latchData + false, // latchPath + false, // dataOut + true // tokenOut )); + + // FIXME: this probably should be removed, unless Ivan doesn't want to change the behavior + prln("set ilc=1"); + marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD,SetDest.InnerLoopCounter,1)); + prln("send data"); marina.instrIn.fill(SEND_DATA); // expect nothing to come out, because the NOP is executing - dataItems = marina.data.drainMany(10); + dataItems = marina.data.drainMany(2); fatal(dataItems.size()!=0, "Expected no data item(s) to emerge but got at least: "+dataItems.size()+" data items"); prln("send torpedo"); @@ -1749,7 +1780,7 @@ public class MarinaTest { } adjustIndent(-2); - prln("End testTorpedoOnAnInfiniteNop"); + prln("End testTorpedoOnAnInfinite"); } private void testOlcDecrementAtHighSpeed(Marina marina) { @@ -1764,8 +1795,8 @@ public class MarinaTest { // of the OLC will be checked by executing a MOVE with // [olc!=0] as the predicate. - int[] olcs = new int[] { 3 /*, 3, 3, 10, 41*/ }; - int[] decr_amounts = new int[] { 2 /*, 3, 4, 9, 10*/ }; + int[] olcs = new int[] { 3, 3, 3, 10, 41 }; + int[] decr_amounts = new int[] { 2, 3, 4, 9, 9 }; for(int which=0; which=olc ? 0 : 1; dataItems = marina.data.drainMany(2); @@ -1963,8 +1994,11 @@ public class MarinaTest { doOneTest(4); doOneTest(5); doOneTest(1001); + doOneTest(1003); doOneTest(3000); doOneTest(3001); + doOneTest(3003); + doOneTest(3004); doOneTest(3009); doOneTest(3010); doOneTest(3011); @@ -1972,9 +2006,13 @@ public class MarinaTest { doOneTest(3013); doOneTest(3014); doOneTest(3015); + doOneTest(3019); + doOneTest(3020); + doOneTest(3023); // these tests take a while and usually pass doOneTest(1000); + doOneTest(1002); doOneTest(1004); doOneTest(1005); doOneTest(1006); @@ -1982,6 +2020,10 @@ public class MarinaTest { doOneTest(3016); doOneTest(3021); doOneTest(3024); + doOneTest(3025); + + // this takes an insanely long time + doOneTest(3017); break; } @@ -1994,9 +2036,9 @@ public class MarinaTest { // Russell's tests begin with 1000 case 1000: walkOneILC(marina); break; // 20-Apr (+verilog) case 1001: countIlc(marina); break; // 20-Apr (+verilog) - case 1002: countOlc(marina); break; + case 1002: countOlc(marina); break; // 23-Apr (+verilog) - case 1003: sendTorpedo(marina); break; + case 1003: sendTorpedo(marina); break; // 23-Apr (+verilog) [with wor-hack] case 1004: flipIlcBit(marina); break; // 20-Apr (+verilog) case 1005: flipOlcBit(marina); break; // 21-Apr (+verilog) @@ -2007,17 +2049,17 @@ public class MarinaTest { case 3000: sendToken(marina); break; // passes, 24-Mar (+verilog) case 3001: testFlagAB(marina); break; // passes, 08-Apr (+verilog) case 3002: testPredicationOnAB(marina); break; // 22-Apr (+verilog) - case 3003: testFlagC(marina); break; - case 3004: testFlagD(marina); break; + case 3003: testFlagC(marina); break; // 23-Apr (+verilog) + case 3004: testFlagD(marina); break; // 23-Apr (+verilog) case 3005: testRequeueStage0(marina); break; case 3006: testRequeueStage0to1(marina); break; case 3007: testRequeueStage0to1to3to0(marina); break; case 3008: testRequeueStage0to2to3to0(marina); break; - case 3009: testWaitForTail(marina); break; // 22-Apr (+verilog) - //case 3010: testRequeueStageDrop(marina); break; // no longer relevant (behavior changed) + case 3009: testWaitForTail(marina); break; // 22-Apr (+verilog) + case 3010: sendData(marina); break; // passes, 24-Mar (+verilog) case 3011: recvData(marina); break; // 21-Apr (+verilog) case 3012: sendDataWithPath(marina); break; // passes, 13-Apr (+verilog) @@ -2027,15 +2069,15 @@ public class MarinaTest { case 3015: testSendAndRecvToken(marina); break; // 21-Apr (+verilog) case 3016: sendDataIlcInfinite(marina); break; // 22-Apr (+verilog) - case 3017: testFlagTruthTable(marina); break; + case 3017: testFlagTruthTable(marina); break; // 23-Apr (+verilog) - case 3019: setOlcFromDataLatch(marina); break; - case 3020: setIlcFromDataLatch(marina); break; + case 3019: setOlcFromDataLatch(marina); break; // 23-Apr (+verilog) + case 3020: setIlcFromDataLatch(marina); break; // 23-Apr (+verilog) case 3021: recvPath(marina); break; // 22-Apr (+verilog) - case 3022: testILC(marina); break; - case 3023: testTorpedoOnAnInfiniteNop(marina); break; + case 3022: testILC(marina); break; // 23-Apr (+verilog) + case 3023: testTorpedoOnAnInfinite(marina); break; case 3024: testRecvAndSendWalkingOne(marina); break; // 21-Apr (+verilog) - case 3025: testOlcDecrementAtHighSpeed(marina); break; + case 3025: testOlcDecrementAtHighSpeed(marina); break; // 23-Apr (+verilog) default: fatal(true, "Test number: "+testNum+" doesn't exist."); -- 1.7.10.4