From 71f6cc6bd7e38d95ed845eb507321c37b2661d1c Mon Sep 17 00:00:00 2001
From: rkao <rkao>
Date: Thu, 30 Oct 2008 17:57:31 +0000
Subject: [PATCH] schematics updated

---
 testCode/isolatedInDock.spi |  133 +++++++++++++++++++++----------------------
 1 file changed, 64 insertions(+), 69 deletions(-)

diff --git a/testCode/isolatedInDock.spi b/testCode/isolatedInDock.spi
index e5672d4..80a5c1f 100644
--- a/testCode/isolatedInDock.spi
+++ b/testCode/isolatedInDock.spi
@@ -1,8 +1,8 @@
 *** SPICE deck for cell isolatedInDock{sch} from library marina
 *** Created on Fri Sep 05, 2008 15:05:59
 *** Last revised on Thu Sep 11, 2008 14:57:39
-*** Written on Thu Oct 23, 2008 16:23:29 by Electric VLSI Design System, 
-*version 8.08i
+*** Written on Thu Oct 30, 2008 09:16:52 by Electric VLSI Design System, 
+*version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
 .OPTIONS NOMOD NOPAGE
@@ -428,52 +428,52 @@ XPMOS@1 out inb vdd PMOSx-X_25
 Xnms2@0 out ina inb nms2-X_25
 .ENDS nand2-X_25
 
-*** CELL: arbiterJ:halfArb{sch}
-.SUBCKT halfArb cross grant[B] inA req[B]
+*** CELL: arbiterK:half2inArb{sch}
+.SUBCKT half2inArb cross grant[B] inA req[B]
 XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10
 XPMOSx@0 cross inA grant[B] NMOSx-X_10
 Xnor2n@0 inA req[B] cross nand2-X_25
-.ENDS halfArb
+.ENDS half2inArb
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-853_7-R_34_667m a b
-Ccap@0 gnd net@14 3.13f
-Ccap@1 gnd net@8 3.13f
-Ccap@2 gnd net@11 3.13f
-Rres@0 net@14 a 4.932
-Rres@1 net@11 net@14 9.865
-Rres@2 b net@8 4.932
-Rres@3 net@8 net@11 9.865
-.ENDS wire-C_0_011f-853_7-R_34_667m
+.SUBCKT wire-C_0_011f-830_7-R_34_667m a b
+Ccap@0 gnd net@14 3.046f
+Ccap@1 gnd net@8 3.046f
+Ccap@2 gnd net@11 3.046f
+Rres@0 net@14 a 4.8
+Rres@1 net@11 net@14 9.599
+Rres@2 b net@8 4.8
+Rres@3 net@8 net@11 9.599
+.ENDS wire-C_0_011f-830_7-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-853_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-853_7-R_34_667m
-.ENDS wire90-853_7-layer_1-width_3
+.SUBCKT wire90-830_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-830_7-R_34_667m
+.ENDS wire90-830_7-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-857_6-R_34_667m a b
-Ccap@0 gnd net@14 3.145f
-Ccap@1 gnd net@8 3.145f
-Ccap@2 gnd net@11 3.145f
-Rres@0 net@14 a 4.955
-Rres@1 net@11 net@14 9.91
-Rres@2 b net@8 4.955
-Rres@3 net@8 net@11 9.91
-.ENDS wire-C_0_011f-857_6-R_34_667m
+.SUBCKT wire-C_0_011f-834_6-R_34_667m a b
+Ccap@0 gnd net@14 3.06f
+Ccap@1 gnd net@8 3.06f
+Ccap@2 gnd net@11 3.06f
+Rres@0 net@14 a 4.822
+Rres@1 net@11 net@14 9.644
+Rres@2 b net@8 4.822
+Rres@3 net@8 net@11 9.644
+.ENDS wire-C_0_011f-834_6-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-857_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-857_6-R_34_667m
-.ENDS wire90-857_6-layer_1-width_3
-
-*** CELL: arbiterJ:arbiterH{sch}
-.SUBCKT arbiterH grant[A] grant[B] req[A] req[B]
-XhalfArb@0 net@12 grant[A] net@5 req[A] halfArb
-XhalfArb@1 net@13 grant[B] net@8 req[B] halfArb
-Xwire90@0 net@12 net@8 wire90-853_7-layer_1-width_3
-Xwire90@1 net@5 net@13 wire90-857_6-layer_1-width_3
-.ENDS arbiterH
+.SUBCKT wire90-834_6-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-834_6-R_34_667m
+.ENDS wire90-834_6-layer_1-width_3
+
+*** CELL: arbiterK:arbiter2{sch}
+.SUBCKT arbiter2 grant[A] grant[B] req[A] req[B]
+XhalfArb@2 net@12 grant[A] net@5 req[A] half2inArb
+XhalfArb@3 net@13 grant[B] net@8 req[B] half2inArb
+Xwire90@0 net@12 net@8 wire90-830_7-layer_1-width_3
+Xwire90@1 net@5 net@13 wire90-834_6-layer_1-width_3
+.ENDS arbiter2
 
 *** CELL: orangeTSMC090nm:NMOSx{sch}
 .SUBCKT NMOSx-X_100 d g s
@@ -1019,7 +1019,7 @@ Xwire@0 a b wire-C_0_011f-1092_8-R_34_667m
 .SUBCKT gaspDrain fire[A] pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] 
 +sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
 +sir[9] soc[1] sor[1] succ
-XarbiterH@3 net@374 net@353 pred net@375 arbiterH
+Xarbiter2@0 net@374 net@353 pred net@375 arbiter2
 Xcenter3i@0 net@241 succ fire[A] ctrAND2in100
 Xinv@0 net@357 net@409 inv-X_10
 Xinv@1 go net@360 inv-X_10
@@ -1647,38 +1647,33 @@ Xwire90@0 net@0 net@2 wire90-6034_2-layer_1-width_3
 +sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] 
 +sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
 +sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] succ
-XaDrainSt@0 net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] net@1[13] net@1[12] 
-+net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] net@1[6] net@1[5] net@1[14] 
-+aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] 
-+aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@1[42] net@1[41] net@1[40] 
-+net@1[39] net@1[38] net@1[37] net@1[36] net@1[35] net@1[34] net@1[33] 
-+net@1[51] net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27] 
-+net@1[26] net@1[25] net@1[24] net@1[23] net@1[50] net@1[22] net@1[21] 
-+net@1[20] net@1[19] net@1[18] net@1[17] net@1[16] net@1[15] net@1[49] 
-+net@1[48] net@1[47] net@1[46] net@1[45] net@1[44] net@1[43] out[10] out[11] 
-+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] 
-+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] 
-+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] 
-+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@13 net@3[8] 
-+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] net@2[8] sir[2] 
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ 
-+drainStage
+XaDrainSt@0 ps[47] ps[48] ps[49] ps[50] ps[51] ps[38] ps[39] ps[40] ps[41] 
++ps[42] ps[43] ps[44] ps[45] ps[46] ps[T] aout[10] aout[11] aout[12] aout[13] 
++aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] 
++aout[9] aout[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] 
++ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27] 
++ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[37] 
++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] out[10] out[11] out[12] out[13] 
++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] 
++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] 
++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] 
++out[5] out[6] out[7] out[8] out[9] net@13 net@3[8] sic[2] sic[3] sic[4] 
++sic[5] sic[6] sic[7] sic[8] sic[9] net@2[8] sir[2] sir[3] sir[4] sir[5] 
++sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ drainStage
 XaFillSta@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@1[4] net@1[3] net@1[2] 
-+net@1[1] net@1[0] net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] 
-+net@1[7] net@1[6] net@1[5] net@1[14] in[10] in[11] in[12] in[13] in[14] 
-+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] 
-+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] 
-+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] net@1[42] 
-+net@1[41] net@1[40] net@1[39] net@1[38] net@1[37] net@1[36] net@1[35] 
-+net@1[34] net@1[33] net@1[51] net@1[32] net@1[31] net@1[30] net@1[29] 
-+net@1[28] net@1[27] net@1[26] net@1[25] net@1[24] net@1[23] net@1[50] 
-+net@1[22] net@1[21] net@1[20] net@1[19] net@1[18] net@1[17] net@1[16] 
-+net@1[15] net@1[49] net@1[48] net@1[47] net@1[46] net@1[45] net@1[44] 
-+net@1[43] pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] 
-+sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] 
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@3[8] sod[1] sod[2] 
-+sod[3] sod[4] sod[5] net@2[8] net@13 fillStage
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] ps[47] ps[48] ps[49] ps[50] 
++ps[51] ps[38] ps[39] ps[40] ps[41] ps[42] ps[43] ps[44] ps[45] ps[46] ps[T] 
++in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] 
++in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] 
++in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] in[4] in[5] 
++in[6] in[7] in[8] in[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] 
++ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] 
++ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] 
++ps[37] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] pred sic[1] sic[2] sic[3] 
++sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] 
++sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] net@3[8] sod[1] sod[2] sod[3] sod[4] sod[5] net@2[8] net@13 
++fillStage
 .ENDS properStopper
 
 *** CELL: scanJ:scanEx1vertA{sch}
-- 
1.7.10.4