From 7e14488b67d1be815780ba58335f0217eeecf0ca Mon Sep 17 00:00:00 2001 From: adam Date: Tue, 6 Feb 2007 13:30:29 +0100 Subject: [PATCH] enable secondary icache, fix icache bug --- src/edu/berkeley/fleet/slipway/Slipway.java | 2 +- src/edu/berkeley/fleet/slipway/dcache.v | 41 +++++++++++++++++++++++-- src/edu/berkeley/fleet/slipway/icache.v | 44 ++++++++++++++++----------- 3 files changed, 66 insertions(+), 21 deletions(-) diff --git a/src/edu/berkeley/fleet/slipway/Slipway.java b/src/edu/berkeley/fleet/slipway/Slipway.java index c70f9c1..a161a02 100644 --- a/src/edu/berkeley/fleet/slipway/Slipway.java +++ b/src/edu/berkeley/fleet/slipway/Slipway.java @@ -27,7 +27,7 @@ public class Slipway extends Interpreter { createShip("Fifo", "fifo3"); createShip("Fifo", "fifo4"); createShip("Icache", "icache1"); - createShip("Icache", "icache2"); + createShip("Icache", "icache2"); createShip("Dcache", "dcache1"); createShip("Dcache", "dcache2"); } diff --git a/src/edu/berkeley/fleet/slipway/dcache.v b/src/edu/berkeley/fleet/slipway/dcache.v index 5e61efc..ccea08b 100644 --- a/src/edu/berkeley/fleet/slipway/dcache.v +++ b/src/edu/berkeley/fleet/slipway/dcache.v @@ -1,5 +1,5 @@ `include "macros.v" -`define BRAM_ADDR_WIDTH 8 +`define BRAM_ADDR_WIDTH 14 `define BRAM_DATA_WIDTH `DATAWIDTH `define BRAM_NAME dcache_bram `include "bram.inc" @@ -17,14 +17,49 @@ module dcache (clk, `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_) `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d) - `include "cache.inc" + `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d) + `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d) + `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_) + `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d) + + reg bram_we; + wire bram_we_; + assign bram_we_ = bram_we; + wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data; + reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address; + wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address; + reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data; + wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_; + assign bram_write_data_ = bram_write_data; + `BRAM_NAME mybram(clk, + bram_we_, bram_write_address, + bram_read_address, bram_write_data_, + not_connected, bram_read_data); + + reg send_done; reg have_read; initial have_read = 0; reg read_pending; initial read_pending = 0; assign bram_read_address = read_addr_d; always @(posedge clk) begin - `include "cache_write.inc" + bram_we = 0; + if (send_done) begin + `onwrite(write_done_r, write_done_a) + send_done = 0; + end + end else begin + if (!write_addr_r && write_addr_a) write_addr_a = 0; + if (!write_data_r && write_data_a) write_data_a = 0; + if (write_addr_r && write_data_r) begin + write_addr_a = 1; + write_data_a = 1; + bram_we = 1; + send_done = 1; + bram_write_address = write_addr_d; + bram_write_data = write_data_d; + end + end if (read_pending) begin read_pending <= 0; diff --git a/src/edu/berkeley/fleet/slipway/icache.v b/src/edu/berkeley/fleet/slipway/icache.v index eb1ef48..637157d 100644 --- a/src/edu/berkeley/fleet/slipway/icache.v +++ b/src/edu/berkeley/fleet/slipway/icache.v @@ -1,5 +1,5 @@ `include "macros.v" -`define BRAM_ADDR_WIDTH 8 +`define BRAM_ADDR_WIDTH 14 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH `define BRAM_NAME icache_bram `include "bram.inc" @@ -33,6 +33,8 @@ module icache (clk, reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos; reg [(`BRAM_ADDR_WIDTH-1):0] preload_size; + initial preload_size = 0; + reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from; reg [(`BRAM_ADDR_WIDTH-1):0] temp_base; reg [(`CODEBAG_SIZE_BITS-1):0] temp_size; @@ -54,17 +56,23 @@ module icache (clk, reg command_valid_read; + reg launched; + initial launched = 0; + + icache_bram mybram(clk, write_flag, write_addr, current_instruction_read_from, write_data, not_connected, ramread); + always @(posedge clk) begin - if (command_valid_read) begin - command_valid <= 1; - command <= ramread; - end + write_flag <= 0; if (!write_addr_r && write_addr_a) write_addr_a = 0; if (!write_data_r && write_data_a) write_data_a = 0; - if (send_done) begin + if (command_valid_read) begin + command_valid_read <= 0; + command_valid <= 1; + + end else if (send_done) begin `onwrite(write_done_r, write_done_a) send_done <= 0; end @@ -73,9 +81,9 @@ module icache (clk, write_addr_a = 1; write_data_a = 1; send_done <= 1; - write_flag = 1; - write_addr = write_addr_d; - write_data = write_data_d; + write_flag <= 1; + write_addr <= write_addr_d; + write_data <= write_data_d; end else if (ihorn_full) begin `onwrite(ihorn_r, ihorn_a) @@ -89,6 +97,7 @@ module icache (clk, end else if (command_valid) begin command_valid <= 0; + command = ramread; case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)]) 0: begin ihorn_full <= 1; @@ -117,9 +126,8 @@ module icache (clk, endcase end else if (cbd_pos < cbd_size) begin - command_valid <= 1; - current_instruction_read_from = cbd_base+cbd_pos; - command <= ram[current_instruction_read_from]; + current_instruction_read_from <= cbd_base+cbd_pos; + command_valid_read <= 1; cbd_pos <= cbd_pos + 1; end else begin @@ -132,10 +140,10 @@ module icache (clk, `onread(preload_r, preload_a) if (preload_size == 0) begin preload_size <= preload_d; - end else begin - write_flag = 1; - write_data = preload_d; - write_addr = preload_pos; + end else if (!launched) begin + write_flag <= 1; + write_data <= preload_d; + write_addr <= preload_pos; if (preload_pos == 0) begin temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)]; temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0]; @@ -144,17 +152,19 @@ module icache (clk, cbd_pos <= 0; cbd_base <= temp_base; cbd_size <= temp_size; + launched <= 1; end preload_pos <= preload_pos + 1; end end end end - +/* if (write_flag) begin write_flag = 0; ram[write_addr] <= write_data; end +*/ end endmodule -- 1.7.10.4