From 879217ecadd1341024234bc3b88d3e1b71627360 Mon Sep 17 00:00:00 2001
From: megacz <adam@megacz.com>
Date: Sat, 7 Mar 2009 14:11:58 -0800
Subject: [PATCH] remove old ucfs

---
 src/edu/berkeley/fleet/fpga/main-ml410.ucf |  223 ----------------------------
 src/edu/berkeley/fleet/fpga/main-ml50x.ucf |  223 ----------------------------
 2 files changed, 446 deletions(-)
 delete mode 100644 src/edu/berkeley/fleet/fpga/main-ml410.ucf
 delete mode 100644 src/edu/berkeley/fleet/fpga/main-ml50x.ucf

diff --git a/src/edu/berkeley/fleet/fpga/main-ml410.ucf b/src/edu/berkeley/fleet/fpga/main-ml410.ucf
deleted file mode 100644
index cd14662..0000000
--- a/src/edu/berkeley/fleet/fpga/main-ml410.ucf
+++ /dev/null
@@ -1,223 +0,0 @@
-## Clock, Reset ##############################################################################
-
-Net clk_pin LOC=J16;
-Net clk_pin IOSTANDARD = LVCMOS25;
-
-Net rst_pin LOC=H7;
-Net rst_pin PULLUP;
-Net rst_pin IOSTANDARD = LVCMOS33;
-
-Net clk_pin TNM_NET = clk_pin;
-TIMESPEC TS_clk_pin = PERIOD clk_pin 10 ns HIGH 50%;
-
-Net clk_unbuffered TNM_NET = clk_unbuffered;
-TIMESPEC TS_clk_unbuffered = PERIOD clk_unbuffered 20 ns;
-
-Net rst_pin TIG;
-
-## UART ##############################################################################
-
-#Net uart_cts LOC=G6;
-#Net uart_cts IOSTANDARD = LVCMOS33;
-#Net uart_cts TIG;
-
-#Net uart_rts LOC=F6;
-#Net uart_rts IOSTANDARD = LVCMOS33;
-#Net uart_rts TIG;
-
-Net uart_in LOC=E6;
-Net uart_in IOSTANDARD = LVCMOS33;
-Net uart_in TIG;
-Net uart_in PULLUP;
-
-Net uart_out LOC=D6;
-Net uart_out IOSTANDARD = LVCMOS33;
-Net uart_out TIG;
-Net uart_out PULLUP;
-
-## VGA ##############################################################################
-
-net "vga_hsync" loc   = f9;
-net "vga_hsync" slew  = slow;
-net "vga_hsync" drive = 2;
-
-net "vga_vsync" loc   = h10;
-net "vga_vsync" slew  = slow;
-net "vga_vsync" drive = 2;
-
-net "vga_clkout"  loc ="c12";
-net "vga_clkout"  slew = fast;
-net "vga_clkout"  drive = 8;
-
-net "vga_r<7>" loc ="h8";
-net "vga_r<6>" loc ="c5";
-net "vga_r<5>" loc ="h9";
-net "vga_r<4>" loc ="g12";
-net "vga_r<3>" loc ="g11";
-net "vga_r<2>" loc ="g10";
-net "vga_r<1>" loc ="f11";
-net "vga_r<0>" loc ="f10";
-net "vga_r<*>" slew = slow;
-net "vga_r<*>" drive = 2;
-
-net "vga_g<7>" loc ="d5";
-net "vga_g<6>" loc ="d4";
-net "vga_g<5>" loc ="f8";
-net "vga_g<4>" loc ="e13";
-net "vga_g<3>" loc ="e12";
-net "vga_g<2>" loc ="e11";
-net "vga_g<1>" loc ="e9";
-net "vga_g<0>" loc ="e8";
-net "vga_g<*>" slew = slow;
-net "vga_g<*>" drive = 2;
-
-net "vga_b<7>" loc ="c4";
-net "vga_b<6>" loc ="c3";
-net "vga_b<5>" loc ="d12";
-net "vga_b<4>" loc ="d11";
-net "vga_b<3>" loc ="d10";
-net "vga_b<2>" loc ="d9";
-net "vga_b<1>" loc ="c13";
-net "vga_b<0>" loc ="g8";
-net "vga_b<*>" slew = slow;
-net "vga_b<*>" drive = 2;
-
-net "vga_*" iostandard = lvcmos33;
-
-## DRAM ##############################################################################
-
-NET "clk_pin"               TNM="SYS_CLK";
-#NET "*/*/clkgen/write_clk_u"    TNM="WRITE_CLK";
-#NET "*/*/clkgen/write_clk90_u"  TNM="WRITE_CLK";
-#NET "*/*/clkgen/read_clk_u"     TNM="READ_CLK";
-#TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG;
-#TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG;
-#TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG;
-#TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG;
-#TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG;
-#TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG;
-
-Net ddr1_Addr_pin<12> LOC=J24;
-Net ddr1_Addr_pin<12> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<11> LOC=K26;
-Net ddr1_Addr_pin<11> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<10> LOC=K24;
-Net ddr1_Addr_pin<10> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<9> LOC=K23;
-Net ddr1_Addr_pin<9> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<8> LOC=L26;
-Net ddr1_Addr_pin<8> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<7> LOC=L25;
-Net ddr1_Addr_pin<7> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<6> LOC=L24;
-Net ddr1_Addr_pin<6> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<5> LOC=M23;
-Net ddr1_Addr_pin<5> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<4> LOC=N24;
-Net ddr1_Addr_pin<4> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<3> LOC=N23;
-Net ddr1_Addr_pin<3> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<2> LOC=N22;
-Net ddr1_Addr_pin<2> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<1> LOC=P22;
-Net ddr1_Addr_pin<1> IOSTANDARD = SSTL2_I;
-Net ddr1_Addr_pin<0> LOC=P24;
-Net ddr1_Addr_pin<0> IOSTANDARD = SSTL2_I;
-Net ddr1_BankAddr_pin<1> LOC=J26;
-Net ddr1_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
-Net ddr1_BankAddr_pin<0> LOC=J25;
-Net ddr1_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
-Net ddr1_CAS_n_pin LOC=D26;
-Net ddr1_CAS_n_pin IOSTANDARD = SSTL2_I;
-Net ddr1_CE_pin LOC=H14;
-Net ddr1_CE_pin IOSTANDARD = SSTL2_I;
-Net ddr1_CS_n_pin LOC=C27;
-Net ddr1_CS_n_pin IOSTANDARD = SSTL2_I;
-Net ddr1_RAS_n_pin LOC=D27;
-Net ddr1_RAS_n_pin IOSTANDARD = SSTL2_I;
-Net ddr1_WE_n_pin LOC=E27;
-Net ddr1_WE_n_pin IOSTANDARD = SSTL2_I;
-Net ddr1_DM_pin<0> LOC=F21;
-Net ddr1_DM_pin<0> IOSTANDARD = SSTL2_II;
-Net ddr1_DM_pin<1> LOC=G22;
-Net ddr1_DM_pin<1> IOSTANDARD = SSTL2_II;
-Net ddr1_DM_pin<2> LOC=E23;
-Net ddr1_DM_pin<2> IOSTANDARD = SSTL2_II;
-Net ddr1_DM_pin<3> LOC=G23;
-Net ddr1_DM_pin<3> IOSTANDARD = SSTL2_II;
-Net ddr1_DQS<0> LOC=F20;
-Net ddr1_DQS<0> IOSTANDARD = SSTL2_II;
-Net ddr1_DQS<1> LOC=G20;
-Net ddr1_DQS<1> IOSTANDARD = SSTL2_II;
-Net ddr1_DQS<2> LOC=G25;
-Net ddr1_DQS<2> IOSTANDARD = SSTL2_II;
-Net ddr1_DQS<3> LOC=F25;
-Net ddr1_DQS<3> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<0> LOC=E17;
-Net ddr1_DQ<0> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<1> LOC=E18;
-Net ddr1_DQ<1> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<2> LOC=F18;
-Net ddr1_DQ<2> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<3> LOC=G18;
-Net ddr1_DQ<3> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<4> LOC=F19;
-Net ddr1_DQ<4> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<5> LOC=E19;
-Net ddr1_DQ<5> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<6> LOC=D21;
-Net ddr1_DQ<6> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<7> LOC=E21;
-Net ddr1_DQ<7> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<8> LOC=G21;
-Net ddr1_DQ<8> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<9> LOC=H20;
-Net ddr1_DQ<9> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<10> LOC=J20;
-Net ddr1_DQ<10> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<11> LOC=J21;
-Net ddr1_DQ<11> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<12> LOC=K21;
-Net ddr1_DQ<12> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<13> LOC=L21;
-Net ddr1_DQ<13> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<14> LOC=J22;
-Net ddr1_DQ<14> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<15> LOC=H22;
-Net ddr1_DQ<15> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<16> LOC=C22;
-Net ddr1_DQ<16> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<17> LOC=C23;
-Net ddr1_DQ<17> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<18> LOC=C24;
-Net ddr1_DQ<18> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<19> LOC=C25;
-Net ddr1_DQ<19> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<20> LOC=D22;
-Net ddr1_DQ<20> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<21> LOC=D24;
-Net ddr1_DQ<21> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<22> LOC=D25;
-Net ddr1_DQ<22> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<23> LOC=C28;
-Net ddr1_DQ<23> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<24> LOC=F23;
-Net ddr1_DQ<24> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<25> LOC=F24;
-Net ddr1_DQ<25> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<26> LOC=F26;
-Net ddr1_DQ<26> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<27> LOC=G26;
-Net ddr1_DQ<27> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<28> LOC=H25;
-Net ddr1_DQ<28> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<29> LOC=H24;
-Net ddr1_DQ<29> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<30> LOC=E24;
-Net ddr1_DQ<30> IOSTANDARD = SSTL2_II;
-Net ddr1_DQ<31> LOC=E22;
-Net ddr1_DQ<31> IOSTANDARD = SSTL2_II;
-Net ddr1_Clk_pin LOC=F28;
-Net ddr1_Clk_pin IOSTANDARD = SSTL2_II;
-Net ddr1_Clk_n_pin LOC=E28;
-Net ddr1_Clk_n_pin IOSTANDARD = SSTL2_II;
diff --git a/src/edu/berkeley/fleet/fpga/main-ml50x.ucf b/src/edu/berkeley/fleet/fpga/main-ml50x.ucf
deleted file mode 100644
index b1c4a03..0000000
--- a/src/edu/berkeley/fleet/fpga/main-ml50x.ucf
+++ /dev/null
@@ -1,223 +0,0 @@
-## Clock, Reset ##############################################################################
-
-Net clk_pin LOC=AH15;
-#Net clk_pin IOSTANDARD = LVCMOS25;
-
-#Net rst_pin LOC=H7;
-#Net rst_pin PULLUP;
-#Net rst_pin IOSTANDARD = LVCMOS33;
-
-Net clk_pin TNM_NET = clk_pin;
-TIMESPEC TS_clk_pin = PERIOD clk_pin 10 ns HIGH 50%;
-
-Net clk_unbuffered TNM_NET = clk_unbuffered;
-TIMESPEC TS_clk_unbuffered = PERIOD clk_unbuffered 20 ns;
-
-Net rst_pin TIG;
-
-## UART ##############################################################################
-
-#Net uart_cts LOC=G6;
-#Net uart_cts IOSTANDARD = LVCMOS33;
-#Net uart_cts TIG;
-
-#Net uart_rts LOC=F6;
-#Net uart_rts IOSTANDARD = LVCMOS33;
-#Net uart_rts TIG;
-
-Net uart_in LOC=AG15;
-#Net uart_in IOSTANDARD = LVCMOS33;
-Net uart_in TIG;
-Net uart_in PULLUP;
-
-Net uart_out LOC=AG20;
-#Net uart_out IOSTANDARD = LVCMOS33;
-Net uart_out TIG;
-Net uart_out PULLUP;
-
-## VGA ##############################################################################
-
-#net "vga_hsync" loc   = f9;
-#net "vga_hsync" slew  = slow;
-#net "vga_hsync" drive = 2;
-#
-#net "vga_vsync" loc   = h10;
-#net "vga_vsync" slew  = slow;
-#net "vga_vsync" drive = 2;
-#
-#net "vga_clkout"  loc ="c12";
-#net "vga_clkout"  slew = fast;
-#net "vga_clkout"  drive = 8;
-#
-#net "vga_r<7>" loc ="h8";
-#net "vga_r<6>" loc ="c5";
-#net "vga_r<5>" loc ="h9";
-#net "vga_r<4>" loc ="g12";
-#net "vga_r<3>" loc ="g11";
-#net "vga_r<2>" loc ="g10";
-#net "vga_r<1>" loc ="f11";
-#net "vga_r<0>" loc ="f10";
-#net "vga_r<*>" slew = slow;
-#net "vga_r<*>" drive = 2;
-#
-#net "vga_g<7>" loc ="d5";
-#net "vga_g<6>" loc ="d4";
-#net "vga_g<5>" loc ="f8";
-#net "vga_g<4>" loc ="e13";
-#net "vga_g<3>" loc ="e12";
-#net "vga_g<2>" loc ="e11";
-#net "vga_g<1>" loc ="e9";
-#net "vga_g<0>" loc ="e8";
-#net "vga_g<*>" slew = slow;
-#net "vga_g<*>" drive = 2;
-#
-#net "vga_b<7>" loc ="c4";
-#net "vga_b<6>" loc ="c3";
-#net "vga_b<5>" loc ="d12";
-#net "vga_b<4>" loc ="d11";
-#net "vga_b<3>" loc ="d10";
-#net "vga_b<2>" loc ="d9";
-#net "vga_b<1>" loc ="c13";
-#net "vga_b<0>" loc ="g8";
-#net "vga_b<*>" slew = slow;
-#net "vga_b<*>" drive = 2;
-#
-#net "vga_*" iostandard = lvcmos33;
-#
-### DRAM ##############################################################################
-
-NET "clk_pin"               TNM="SYS_CLK";
-#NET "*/*/clkgen/write_clk_u"    TNM="WRITE_CLK";
-#NET "*/*/clkgen/write_clk90_u"  TNM="WRITE_CLK";
-#NET "*/*/clkgen/read_clk_u"     TNM="READ_CLK";
-#TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG;
-#TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG;
-#TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG;
-#TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG;
-#TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG;
-#TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG;
-
-#Net ddr1_Addr_pin<12> LOC=J24;
-#Net ddr1_Addr_pin<12> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<11> LOC=K26;
-#Net ddr1_Addr_pin<11> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<10> LOC=K24;
-#Net ddr1_Addr_pin<10> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<9> LOC=K23;
-#Net ddr1_Addr_pin<9> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<8> LOC=L26;
-#Net ddr1_Addr_pin<8> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<7> LOC=L25;
-#Net ddr1_Addr_pin<7> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<6> LOC=L24;
-#Net ddr1_Addr_pin<6> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<5> LOC=M23;
-#Net ddr1_Addr_pin<5> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<4> LOC=N24;
-#Net ddr1_Addr_pin<4> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<3> LOC=N23;
-#Net ddr1_Addr_pin<3> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<2> LOC=N22;
-#Net ddr1_Addr_pin<2> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<1> LOC=P22;
-#Net ddr1_Addr_pin<1> IOSTANDARD = SSTL2_I;
-#Net ddr1_Addr_pin<0> LOC=P24;
-#Net ddr1_Addr_pin<0> IOSTANDARD = SSTL2_I;
-#Net ddr1_BankAddr_pin<1> LOC=J26;
-#Net ddr1_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
-#Net ddr1_BankAddr_pin<0> LOC=J25;
-#Net ddr1_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
-#Net ddr1_CAS_n_pin LOC=D26;
-#Net ddr1_CAS_n_pin IOSTANDARD = SSTL2_I;
-#Net ddr1_CE_pin LOC=H14;
-#Net ddr1_CE_pin IOSTANDARD = SSTL2_I;
-#Net ddr1_CS_n_pin LOC=C27;
-#Net ddr1_CS_n_pin IOSTANDARD = SSTL2_I;
-#Net ddr1_RAS_n_pin LOC=D27;
-#Net ddr1_RAS_n_pin IOSTANDARD = SSTL2_I;
-#Net ddr1_WE_n_pin LOC=E27;
-#Net ddr1_WE_n_pin IOSTANDARD = SSTL2_I;
-#Net ddr1_DM_pin<0> LOC=F21;
-#Net ddr1_DM_pin<0> IOSTANDARD = SSTL2_II;
-#Net ddr1_DM_pin<1> LOC=G22;
-#Net ddr1_DM_pin<1> IOSTANDARD = SSTL2_II;
-#Net ddr1_DM_pin<2> LOC=E23;
-#Net ddr1_DM_pin<2> IOSTANDARD = SSTL2_II;
-#Net ddr1_DM_pin<3> LOC=G23;
-#Net ddr1_DM_pin<3> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQS<0> LOC=F20;
-#Net ddr1_DQS<0> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQS<1> LOC=G20;
-#Net ddr1_DQS<1> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQS<2> LOC=G25;
-#Net ddr1_DQS<2> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQS<3> LOC=F25;
-#Net ddr1_DQS<3> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<0> LOC=E17;
-#Net ddr1_DQ<0> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<1> LOC=E18;
-#Net ddr1_DQ<1> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<2> LOC=F18;
-#Net ddr1_DQ<2> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<3> LOC=G18;
-#Net ddr1_DQ<3> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<4> LOC=F19;
-#Net ddr1_DQ<4> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<5> LOC=E19;
-#Net ddr1_DQ<5> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<6> LOC=D21;
-#Net ddr1_DQ<6> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<7> LOC=E21;
-#Net ddr1_DQ<7> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<8> LOC=G21;
-#Net ddr1_DQ<8> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<9> LOC=H20;
-#Net ddr1_DQ<9> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<10> LOC=J20;
-#Net ddr1_DQ<10> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<11> LOC=J21;
-#Net ddr1_DQ<11> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<12> LOC=K21;
-#Net ddr1_DQ<12> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<13> LOC=L21;
-#Net ddr1_DQ<13> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<14> LOC=J22;
-#Net ddr1_DQ<14> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<15> LOC=H22;
-#Net ddr1_DQ<15> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<16> LOC=C22;
-#Net ddr1_DQ<16> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<17> LOC=C23;
-#Net ddr1_DQ<17> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<18> LOC=C24;
-#Net ddr1_DQ<18> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<19> LOC=C25;
-#Net ddr1_DQ<19> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<20> LOC=D22;
-#Net ddr1_DQ<20> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<21> LOC=D24;
-#Net ddr1_DQ<21> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<22> LOC=D25;
-#Net ddr1_DQ<22> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<23> LOC=C28;
-#Net ddr1_DQ<23> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<24> LOC=F23;
-#Net ddr1_DQ<24> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<25> LOC=F24;
-#Net ddr1_DQ<25> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<26> LOC=F26;
-#Net ddr1_DQ<26> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<27> LOC=G26;
-#Net ddr1_DQ<27> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<28> LOC=H25;
-#Net ddr1_DQ<28> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<29> LOC=H24;
-#Net ddr1_DQ<29> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<30> LOC=E24;
-#Net ddr1_DQ<30> IOSTANDARD = SSTL2_II;
-#Net ddr1_DQ<31> LOC=E22;
-#Net ddr1_DQ<31> IOSTANDARD = SSTL2_II;
-#Net ddr1_Clk_pin LOC=F28;
-#Net ddr1_Clk_pin IOSTANDARD = SSTL2_II;
-#Net ddr1_Clk_n_pin LOC=E28;
-#Net ddr1_Clk_n_pin IOSTANDARD = SSTL2_II;
-- 
1.7.10.4