From a11ebfe9d4cccd7ec8a314521249c856cc33a18b Mon Sep 17 00:00:00 2001 From: megacz Date: Mon, 29 Dec 2008 17:42:43 -0800 Subject: [PATCH] remove use of uart_rts and uart_cts in ships/Debug, and overhaul it --- ships/Debug.ship | 179 +++++++++++++++++++----------------------------------- 1 file changed, 64 insertions(+), 115 deletions(-) diff --git a/ships/Debug.ship b/ships/Debug.ship index a2076f1..549633c 100644 --- a/ships/Debug.ship +++ b/ships/Debug.ship @@ -1,15 +1,11 @@ ship: Debug == Ports =========================================================== -data in: in +data in: in +dockless out: out -percolate up: root_in_r 1 -percolate down: root_in_a 1 -percolate up: root_in_d 8 percolate down: uart_in 1 percolate up: uart_out 1 -percolate up: uart_rts 1 -percolate down: uart_cts 1 percolate up: rst_out 1 percolate down: rst_in 1 @@ -17,6 +13,9 @@ percolate down: rst_in 1 == TeX ============================================================== +percolate up: uart_rts 1 +percolate down: uart_cts 1 + This ship is used for debugging. It has only one port, {\tt in}. Programmers should send debug report values to this port. How such values are reported back to the programmer doing the debugging is left @@ -42,34 +41,32 @@ public void service() { wire break_i; reg break_last; - reg send_k; initial send_k = 0; + reg send_k; + initial send_k = 0; - wire data_to_host_full; - wire data_to_host_write_enable; - wire [7:0] data_to_host; + reg [`WORDWIDTH-1:0] data_to_host_full_word; + reg [7:0] count_in; + reg [7:0] count_out; + reg [49:0] out_d; + assign out_d_ = out_d; + wire data_to_host_full; + reg [7:0] data_to_host; wire data_to_fleet_empty; - wire data_to_fleet_read_enable; wire [7:0] data_to_fleet; - - reg we; - reg re; - reg [7:0] data_to_host_r; - assign data_to_host = data_to_host_r; - - wire ser_rst; - reg ser_rst_r; - initial ser_rst_r = 0; - assign ser_rst = (rst_in & ser_rst_r); + reg data_to_host_write_enable; + reg data_to_fleet_read_enable; wire sio_ce; wire sio_ce_x4; wire break; + wire uart_cts; + assign uart_cts = 0; assign rst_out = rst_in && !break; - sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4); - sasc_top sasc_top(clk, ser_rst, + sasc_brg sasc_brg(clk, rst_in, 3, 65, sio_ce, sio_ce_x4); + sasc_top sasc_top(clk, rst_in, uart_in, uart_out, uart_cts, @@ -90,100 +87,52 @@ public void service() { assign break_i = break && !break_last; assign break_done = !break && break_last; - reg data_to_host_write_enable_reg; - reg data_to_fleet_read_enable_reg; - - reg [`WORDWIDTH-1:0] root_out_d; - reg root_out_r; initial root_out_r = 0; - wire root_out_a; - - reg root_out_a_reg; - reg root_in_r_reg; - reg [7:0] root_in_d_reg; - initial root_in_r_reg = 0; - initial root_in_d_reg = 0; - initial root_out_a_reg = 0; - initial data_to_fleet_read_enable_reg = 0; - initial data_to_host_write_enable_reg = 0; - - assign root_out_a = root_out_a_reg; - assign root_in_r = root_in_r_reg; - assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg; - assign data_to_host_write_enable = data_to_host_write_enable_reg; - assign root_in_d = root_in_d_reg; - // fpga -> host - always @(posedge clk) - begin - if (break_i) begin - root_out_a_reg = 0; - data_to_host_write_enable_reg <= 0; - - end else if (break_done) begin - data_to_host_write_enable_reg <= 1; - data_to_host_r <= 111; - send_k <= 1; - end else if (send_k) begin - data_to_host_write_enable_reg <= 1; - data_to_host_r <= 107; - send_k <= 0; - - - end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin - data_to_host_write_enable_reg <= 1; - data_to_host_r <= root_out_d[7:0]; - root_out_a_reg = 1; - end else if (root_out_a_reg && !root_out_r) begin - data_to_host_write_enable_reg <= 0; - root_out_a_reg = 0; - end else begin - data_to_host_write_enable_reg <= 0; - end - end - - // host -> fpga - always @(posedge clk) - begin - ser_rst_r <= 1; - if (break_i) begin - root_in_r_reg <= 0; - root_in_d_reg <= 0; - data_to_fleet_read_enable_reg <= 0; - end else - - if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin - root_in_r_reg <= 1; - root_in_d_reg <= data_to_fleet; - data_to_fleet_read_enable_reg <= 1; + always @(posedge clk) begin + if (!rst) begin + count_in <= 0; + count_out <= 0; + `reset end else begin - data_to_fleet_read_enable_reg <= 0; - if (root_in_a) begin - root_in_r_reg <= 0; - end - end - end - - reg [7:0] count; - initial count = 0; - - always @(posedge clk) begin - if (!rst) begin - `reset - end else begin - `flush - `cleanup - if (root_out_r && root_out_a) root_out_r <= 0; - if (`in_full && !root_out_r && !root_out_a && count==0) begin - `drain_in - root_out_d <= in_d; - root_out_r <= 1; - count <= 5; - end - if (count!=0 && !root_out_r && !root_out_a) begin - count <= count-1; - root_out_r <= 1; - root_out_d <= (root_out_d >> 8); - end + + `flush + `cleanup + + // fpga -> host + data_to_host_write_enable <= 0; + if (break_i) begin + end else if (break_done) begin + data_to_host_write_enable <= 1; + data_to_host <= 111; + send_k <= 1; + end else if (send_k) begin + data_to_host_write_enable <= 1; + data_to_host <= 107; + send_k <= 0; + end else if (count_out==0 && `in_full) begin + `drain_in + data_to_host_full_word <= in_d; + count_out <= 6; + end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable) begin + data_to_host <= data_to_host_full_word[7:0]; + data_to_host_full_word <= (data_to_host_full_word >> 8); + data_to_host_write_enable <= 1; + count_out <= count_out-1; + end + + // host -> fpga + data_to_fleet_read_enable <= 0; + if (!data_to_fleet_empty && `out_empty && !data_to_fleet_read_enable) begin + out_d <= { out_d[41:0], data_to_fleet[7:0] }; + data_to_fleet_read_enable <= 1; + if (count_in==7) begin + count_in <= 0; + `fill_out + end else begin + count_in <= count_in+1; + end + end + end end -- 1.7.10.4