From aee6d6898bdb8294637df4aa0ef824b268c55a01 Mon Sep 17 00:00:00 2001
From: Simon Marlow <marlowsd@gmail.com>
Date: Fri, 6 Feb 2009 13:01:15 +0000
Subject: [PATCH] add a store/load memory barrier

---
 includes/SMP.h |   25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/includes/SMP.h b/includes/SMP.h
index bf23e08..5d74667 100644
--- a/includes/SMP.h
+++ b/includes/SMP.h
@@ -60,6 +60,11 @@ EXTERN_INLINE StgWord cas(StgVolatilePtr p, StgWord o, StgWord n);
  */ 
 EXTERN_INLINE void write_barrier(void);
 
+/*
+ * Prevents loads from moving before earlier stores.
+ */
+EXTERN_INLINE void store_load_barrier(void);
+
 /* ----------------------------------------------------------------------------
    Implementations
    ------------------------------------------------------------------------- */
@@ -180,11 +185,31 @@ write_barrier(void) {
 #endif
 }
 
+EXTERN_INLINE void
+store_load_barrier(void) {
+#if i386_HOST_ARCH
+    __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory");
+#elif x86_64_HOST_ARCH
+    __asm__ __volatile__ ("lock; addq $0,0(%%rsp)" : : : "memory");
+#elif powerpc_HOST_ARCH
+    __asm__ __volatile__ ("msync" : : : "memory");
+#elif sparc_HOST_ARCH
+    /* Sparc in TSO mode does not require write/write barriers. */
+    __asm__ __volatile__ ("membar" : : : "memory");
+#elif !defined(WITHSMP)
+    return;
+#else
+#error memory barriers unimplemented on this architecture
+#endif
+}
+
 /* ---------------------------------------------------------------------- */
 #else /* !THREADED_RTS */
 
 #define write_barrier() /* nothing */
 
+#define store_load_barrier() /* nothing */
+
 INLINE_HEADER StgWord
 xchg(StgPtr p, StgWord w)
 {
-- 
1.7.10.4