From b199f10b007be9d849cef109bb69705018ebd5b9 Mon Sep 17 00:00:00 2001 From: adam Date: Sat, 13 Dec 2008 05:27:51 +0100 Subject: [PATCH] clean up main.ucf --- src/edu/berkeley/fleet/fpga/main.ucf | 67 +++++++++++++++++----------------- 1 file changed, 34 insertions(+), 33 deletions(-) diff --git a/src/edu/berkeley/fleet/fpga/main.ucf b/src/edu/berkeley/fleet/fpga/main.ucf index 478d803..9cc78bb 100644 --- a/src/edu/berkeley/fleet/fpga/main.ucf +++ b/src/edu/berkeley/fleet/fpga/main.ucf @@ -1,17 +1,12 @@ -############################################################################ -## This system.ucf file is generated by Base System Builder based on the -## settings in the selected Xilinx Board Definition file. Please add other -## user constraints to this file based on customer design specifications. -############################################################################ +## Clock, Reset ############################################################################## Net clk_pin LOC=J16; Net clk_pin IOSTANDARD = LVCMOS25; + Net rst_pin LOC=H7; Net rst_pin PULLUP; Net rst_pin IOSTANDARD = LVCMOS33; -### System level constraints - Net clk_pin TNM_NET = clk_pin; TIMESPEC TS_clk_pin = PERIOD clk_pin 10 ns HIGH 50%; @@ -20,16 +15,27 @@ TIMESPEC TS_clk_unbuffered = PERIOD clk_unbuffered 20 ns; Net rst_pin TIG; -NET "clk_pin" TNM="SYS_CLK"; -#NET "*/*/clkgen/write_clk_u" TNM="WRITE_CLK"; -#NET "*/*/clkgen/write_clk90_u" TNM="WRITE_CLK"; -#NET "*/*/clkgen/read_clk_u" TNM="READ_CLK"; -#TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG; -#TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG; -#TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG; -#TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG; -#TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG; -#TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG; +## UART ############################################################################## + +Net uart_cts LOC=G6; +Net uart_cts IOSTANDARD = LVCMOS33; +Net uart_cts TIG; + +Net uart_rts LOC=F6; +Net uart_rts IOSTANDARD = LVCMOS33; +Net uart_rts TIG; + +Net uart_in LOC=E6; +Net uart_in IOSTANDARD = LVCMOS33; +Net uart_in TIG; +Net uart_in PULLUP; + +Net uart_out LOC=D6; +Net uart_out IOSTANDARD = LVCMOS33; +Net uart_out TIG; +Net uart_out PULLUP; + +## VGA ############################################################################## net "vga_hsync" loc = f9; net "vga_hsync" slew = slow; @@ -78,23 +84,18 @@ net "vga_b<*>" drive = 2; net "vga_*" iostandard = lvcmos33; +## DRAM ############################################################################## -Net uart_cts LOC=G6; -Net uart_cts IOSTANDARD = LVCMOS33; -Net uart_cts TIG; -Net uart_rts LOC=F6; -Net uart_rts IOSTANDARD = LVCMOS33; -Net uart_rts TIG; - -Net uart_in LOC=E6; -Net uart_in IOSTANDARD = LVCMOS33; -Net uart_in TIG; -Net uart_in PULLUP; - -Net uart_out LOC=D6; -Net uart_out IOSTANDARD = LVCMOS33; -Net uart_out TIG; -Net uart_out PULLUP; +NET "clk_pin" TNM="SYS_CLK"; +#NET "*/*/clkgen/write_clk_u" TNM="WRITE_CLK"; +#NET "*/*/clkgen/write_clk90_u" TNM="WRITE_CLK"; +#NET "*/*/clkgen/read_clk_u" TNM="READ_CLK"; +#TIMESPEC "TS_SYS_DDRREAD"=FROM "SYS_CLK" TO "WRITE_CLK" TIG; +#TIMESPEC "TS_DDRREAD_SYS"=FROM "WRITE_CLK" TO "SYS_CLK" TIG; +#TIMESPEC "TS_SYS_DDRWRITE"=FROM "SYS_CLK" TO "READ_CLK" TIG; +#TIMESPEC "TS_DDRWRITE_SYS"=FROM "READ_CLK" TO "SYS_CLK" TIG; +#TIMESPEC "TS_DDRREAD_DDRWRITE"=FROM "READ_CLK" TO "WRITE_CLK" TIG; +#TIMESPEC "TS_DDRWRITE_DDRREAD"=FROM "WRITE_CLK" TO "READ_CLK" TIG; Net ddr1_Addr_pin<12> LOC=J24; Net ddr1_Addr_pin<12> IOSTANDARD = SSTL2_I; -- 1.7.10.4