From ba501e57029a321255a75f8ae0dcb0d0a487b4b6 Mon Sep 17 00:00:00 2001 From: megacz Date: Sun, 1 Mar 2009 08:18:43 -0800 Subject: [PATCH] more predictable instance naming in Verilog.java --- src/edu/berkeley/fleet/fpga/verilog/Verilog.java | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java index 3ac807f..04985ff 100644 --- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java +++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java @@ -628,7 +628,17 @@ public class Verilog { public InstantiatedModule(Module thisModule, Module module) { this.thisModule = thisModule; this.module = module; - this.id = thisModule.id++; + // CRUDE + int id = 0; + OUTER: while(true) { + for (InstantiatedModule im : thisModule.instantiatedModules) + if (im.getName().equals(module.getName()+"_"+id)) { + id++; + continue OUTER; + } + break; + } + this.id = id; thisModule.instantiatedModules.add(this); for(String s : module.portorder) getPort(s); -- 1.7.10.4