From c98f132ea63bdad8a3427f9ff42c81549320afe5 Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Mon, 20 Apr 2009 18:26:53 +0000 Subject: [PATCH] update some paths, add master clear code for Verilog, partial implementation of get OLC/ILC --- .../com/sun/vlsi/chips/marina/test/Marina.java | 72 ++++++++++++++++---- 1 file changed, 57 insertions(+), 15 deletions(-) diff --git a/testCode/com/sun/vlsi/chips/marina/test/Marina.java b/testCode/com/sun/vlsi/chips/marina/test/Marina.java index 30e2ea9..1e772d2 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/Marina.java +++ b/testCode/com/sun/vlsi/chips/marina/test/Marina.java @@ -5,6 +5,7 @@ import com.sun.async.test.ChainControl; import com.sun.async.test.ChipModel; import com.sun.async.test.JtagTester; import com.sun.async.test.NanosimModel; +import com.sun.async.test.VerilogModel; import edu.berkeley.fleet.api.Instruction; @@ -17,10 +18,14 @@ public class Marina { public static final String CONTROL_CHAIN = "marina.marina_control"; public static final String REPORT_CHAIN = "marina.marina_report"; - private static final String OLC_PATH = - "dataPath@0.ringSkip@1.skipCoun@1.skipCoun@0.scanKx6@0"; - private static final String ILC_PATH = - "dataPath@0.ringSkip@1.skipCoun@1.skipCoun@0.scanKx9@0"; + private static final String OLC_PATH_EVEN = + "outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.scanEx3h@1"; // bits 2,4,6 + private static final String OLC_PATH_ODD = + "outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.scanEx3h@2"; // bits 1,3,5 + private static final String ILC_PATH_ODD = + "outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.scanEx4h@0"; // bits 1,3,5,7 + private static final String ILC_PATH_EVEN = + "outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.scanEx4h@1"; // bits 2,4,6,8 private static final String FLAGS_PATH = "outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flags@0.scanEx3h@0"; @@ -52,7 +57,14 @@ public class Marina { private int value; private Ilc() { shiftReport(true, false); - value = (int) cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH).bitReverse().not().toLong(); + BitVector odd = cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH_ODD).bitReverse().not(); + BitVector even = cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH_EVEN).bitReverse().not(); + BitVector ret = new BitVector(8, "olc"); + for(int i=0; i<4; i++) { + ret.set(i*2, odd.get(i)); + ret.set(i*2+1, even.get(i)); + } + value = (int)ret.toLong(); } /** Get the inner loop counter done bit. */ public boolean getDone() { @@ -118,16 +130,39 @@ public class Marina { } public void masterClear() { final double WIDTH = 10; // ns - NanosimModel nModel = (NanosimModel) model; // Put a high going pulse on the internal chip master clear signal - nModel.setNodeVoltage("sid[9]",1.0); - nModel.setNodeVoltage("sic[9]",1.0); - nModel.setNodeVoltage("sir[9]",1.0); - nModel.waitNS(WIDTH); - nModel.setNodeVoltage("sid[9]",0.0); - nModel.setNodeVoltage("sic[9]",0.0); - nModel.setNodeVoltage("sir[9]",0.0); - nModel.waitNS(1); + if (model instanceof VerilogModel) { + + data.clear(); + instrIn.clear(); + + ((VerilogModel)model).setNodeState("sid[9]", 1); + ((VerilogModel)model).setNodeState("sic[9]", 1); + ((VerilogModel)model).setNodeState("sir[9]", 1); + model.waitNS(WIDTH); + ((VerilogModel)model).setNodeState("sid[9]", 0); + ((VerilogModel)model).setNodeState("sic[9]", 0); + ((VerilogModel)model).setNodeState("sir[9]", 0); + model.waitNS(1); + + // the proper stopper states come up in an undefined ("X") + // state, so under Verilog we need to force them to a + // known state + + data.idle(); + instrIn.idle(); + + } else { + NanosimModel nModel = (NanosimModel) model; + nModel.setNodeVoltage("sid[9]",1.0); + nModel.setNodeVoltage("sic[9]",1.0); + nModel.setNodeVoltage("sir[9]",1.0); + nModel.waitNS(WIDTH); + nModel.setNodeVoltage("sid[9]",0.0); + nModel.setNodeVoltage("sic[9]",0.0); + nModel.setNodeVoltage("sir[9]",0.0); + nModel.waitNS(1); + } resetAfterMasterClear(); } private void resetAfterMasterClear() { @@ -153,7 +188,14 @@ public class Marina { /** Get the 6 bit outer loop counter. */ public int getOLC() { shiftReport(true, false); - return (int) cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH).bitReverse().not().toLong(); + BitVector odd = cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH_ODD).bitReverse().not(); + BitVector even = cc.getOutBits(REPORT_CHAIN+"."+OLC_PATH_EVEN).bitReverse().not(); + BitVector ret = new BitVector(6, "olc"); + for(int i=0; i<3; i++) { + ret.set(i*2, odd.get(i)); + ret.set(i*2+1, even.get(i)); + } + return (int)ret.toLong(); } /** Get the 7 bit inner loop counter. The MSB is the zero bit. * The low order 6 bits are the count */ -- 1.7.10.4