From caa93dc7618f95e403b52ea834fa1f136d26e43d Mon Sep 17 00:00:00 2001 From: adam Date: Mon, 10 Nov 2008 06:54:08 +0100 Subject: [PATCH] adjust ships to use fill/drain/full/empty macros --- {ships => misc/obsolete-ships}/DDR2.ship | 0 ships/Alu.ship | 36 ++++++-------- ships/CarrySaveAdder.ship | 13 +++-- ships/Counter.ship | 51 +++++++++---------- ships/DRAM.ship | 20 +++----- ships/Debug.ship | 11 +++-- ships/Fifo.ship | 18 +------ ships/Lut3.ship | 20 +++----- ships/Memory.ship | 37 ++++++-------- ships/Rotator.ship | 30 +++++++----- ships/Video.ship | 12 ++--- src/edu/berkeley/fleet/fpga/Fpga.java | 78 +++++++++++++++++++++++++----- 12 files changed, 174 insertions(+), 152 deletions(-) rename {ships => misc/obsolete-ships}/DDR2.ship (100%) diff --git a/ships/DDR2.ship b/misc/obsolete-ships/DDR2.ship similarity index 100% rename from ships/DDR2.ship rename to misc/obsolete-ships/DDR2.ship diff --git a/ships/Alu.ship b/ships/Alu.ship index 2089b8a..6157fc1 100644 --- a/ships/Alu.ship +++ b/ships/Alu.ship @@ -167,29 +167,25 @@ public void service() { `reset end else begin `flush - if (!in1_r_ && in1_a) in1_a <= 0; - if (!in2_r_ && in2_a) in2_a <= 0; - if (!inOp_r_ && inOp_a) inOp_a <= 0; - if (out_r && out_a) begin - out_r <= 0; - inOp_a <= 1; - - if (inOp_d==0) in1_a <= 1; - else if (inOp_d==1) in2_a <= 1; - else if (inOp_d==9 && both_negative) begin in1_a <= 1; in2_a <= 1; end - else if (inOp_d==4 && greater) in1_a <= 1; - else if (inOp_d==5 && greater) in2_a <= 1; - else if (inOp_d==9 && greater) in1_a <= 1; - else if (inOp_d==4 && !greater) in2_a <= 1; - else if (inOp_d==5 && !greater) in1_a <= 1; - else if (inOp_d==9 && !greater) in2_a <= 1; + `cleanup + if (`out_draining) begin + `drain_inOp + if (inOp_d==0) `drain_in1 + else if (inOp_d==1) `drain_in2 + else if (inOp_d==9 && both_negative) begin `drain_in1 `drain_in2 end + else if (inOp_d==4 && greater) `drain_in1 + else if (inOp_d==5 && greater) `drain_in2 + else if (inOp_d==9 && greater) `drain_in1 + else if (inOp_d==4 && !greater) `drain_in2 + else if (inOp_d==5 && !greater) `drain_in1 + else if (inOp_d==9 && !greater) `drain_in2 else begin - in1_a <= 1; - in2_a <= 1; + `drain_in1 + `drain_in2 end end - if (!out_r && !out_a && in1_r && !in1_a && in2_r && !in2_a && inOp_r && !inOp_a) begin - out_r <= 1; + if (`out_empty && `in1_full && `in2_full && `inOp_full) begin + `fill_out end end end diff --git a/ships/CarrySaveAdder.ship b/ships/CarrySaveAdder.ship index 4371afd..dc67fab 100644 --- a/ships/CarrySaveAdder.ship +++ b/ships/CarrySaveAdder.ship @@ -44,13 +44,12 @@ public void service() { state <= 0; end else begin `flush - if (!in_r_ && in_a) in_a <= 0; - if (out_r && out_a) out_r <= 0; - if (!out_r && !out_a && state==3) begin + `cleanup + if (`out_empty && state==3) begin out_d <= { 1'b0, temp }; - out_r <= 1; + `fill_out state <= state + 1; - end else if (in_r && !in_a && !out_r && !out_a) begin + end else if (`in_full && `out_empty) begin if (state == 0) begin out_d <= { 1'b0, in_d }; end else if (state == 1) begin @@ -58,10 +57,10 @@ public void service() { end else if (state == 2) begin out_d <= { majority[`DATAWIDTH-1:0], 1'b0 }; temp <= xors; - out_r <= 1; + `fill_out end state <= state + 1; - in_a <= 1; + `drain_in end end end diff --git a/ships/Counter.ship b/ships/Counter.ship index 91ba0d1..dbdb4a5 100644 --- a/ships/Counter.ship +++ b/ships/Counter.ship @@ -48,50 +48,47 @@ public void service() { } full <= 0; end else begin `flush - if (!in1_r && in1_a) in1_a <= 0; - if (!in2_r && in2_a) in2_a <= 0; - if (!inOp_r && inOp_a) inOp_a <= 0; - if (!inOp_r && !inOp_a) full <= 0; - if (out_r && out_a) begin - out_r <= 0; + `cleanup + if (`inOp_empty) full <= 0; + if (`out_draining) begin if (op_count) temp <= temp - in2_d; else temp <= temp - 1; - if (op_pass && op_v1) in1_a <= 1; - if (op_pass && op_v2) in2_a <= 1; - end else if (inOp_r && !inOp_a) begin + if (op_pass && op_v1) `drain_in1 + if (op_pass && op_v2) `drain_in2 + end else if (`inOp_full) begin if (!full) begin - if (op_count && in1_r && !in1_a && in2_r && !in2_a) begin + if (op_count && `in1_full && `in2_full) begin temp <= in1_d[`DATAWIDTH-1:0] - in2_d[`DATAWIDTH-1:0]; - in1_a <= 1; + `drain_in1 full <= 1; - end else if (op_c1 && in1_r && !in1_a) begin + end else if (op_c1 && `in1_full) begin temp <= in1_d[`DATAWIDTH-1:0]-1; - in1_a <= 1; + `drain_in1 full <= 1; - end else if (op_c2 && in2_r && !in2_a) begin + end else if (op_c2 && `in2_full) begin temp <= in2_d[`DATAWIDTH-1:0]-1; - in2_a <= 1; + `drain_in2 full <= 1; end end else if (temp[`DATAWIDTH-1]) begin full <= 0; - inOp_a <= 1; + `drain_inOp if (op_count) begin - in2_a <= 1; + `drain_in2 end else if (op_repeat && op_v1) begin - in1_a <= 1; + `drain_in1 end else if (op_repeat && op_v2) begin - in2_a <= 1; + `drain_in2 end - end else if (!out_r && !out_a) begin + end else if (`out_empty) begin if (op_count) begin - out_r <= 1; - end else if (op_v1 && in1_r && !in1_a) begin - if (op_drop) begin in1_a <= 1; temp <= temp-1; end - else out_r <= 1; - end else if (op_v2 && in2_r && !in2_a) begin - if (op_drop) begin in2_a <= 1; temp <= temp-1; end - else out_r <= 1; + `fill_out + end else if (op_v1 && `in1_full) begin + if (op_drop) begin `drain_in1 temp <= temp-1; end + else `fill_out + end else if (op_v2 && `in2_full) begin + if (op_drop) begin `drain_in2 temp <= temp-1; end + else `fill_out end end end diff --git a/ships/DRAM.ship b/ships/DRAM.ship index d5d5338..21f572c 100644 --- a/ships/DRAM.ship +++ b/ships/DRAM.ship @@ -42,29 +42,25 @@ data out: out end else begin `flush - - if (!inAddrRead_r_ && inAddrRead_a) inAddrRead_a <= 0; - if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0; - if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0; - if ( out_r && out_a) out_r <= 0; + `cleanup if (dram_addr_r && !dram_addr_a) begin // busy end else if (dram_addr_r && dram_addr_a && !dram_isread) begin dram_addr_r <= 0; - inAddrWrite_a <= 1; - inDataWrite_a <= 1; + `drain_inDataWrite + `drain_inAddrWrite + `fill_out out_d <= { 1'b1, 37'b0 }; - out_r <= 1; end else if (dram_addr_r && dram_addr_a && dram_isread) begin dram_addr_r <= 0; - inAddrRead_a <= 1; + `drain_inAddrRead + `fill_out out_d <= { 1'b0, dram_read_data[36:0] }; - out_r <= 1; - end else if (!out_r && !out_a && inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !dram_addr_r && !dram_addr_a) begin + end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full && !dram_addr_r && !dram_addr_a) begin dram_addr_r <= 1; dram_isread <= 0; - end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a && !dram_addr_r && !dram_addr_a) begin + end else if (`out_empty && `inAddrRead_full && !dram_addr_r && !dram_addr_a) begin dram_addr_r <= 1; dram_isread <= 1; end diff --git a/ships/Debug.ship b/ships/Debug.ship index c3ea67d..e33871f 100644 --- a/ships/Debug.ship +++ b/ships/Debug.ship @@ -30,15 +30,20 @@ public void service() { == FPGA ============================================================== - assign out_d_ = in_d; - assign out_r_ = in_r; + reg [`DATAWIDTH-1:0] out_d; + assign out_d_ = out_d; always @(posedge clk) begin if (!rst) begin `reset end else begin `flush - in_a <= out_a; + `cleanup + if (`in_full && `out_empty) begin + `drain_in + `fill_out + out_d <= in_d; + end end end diff --git a/ships/Fifo.ship b/ships/Fifo.ship index 80dcebc..616c97b 100644 --- a/ships/Fifo.ship +++ b/ships/Fifo.ship @@ -31,23 +31,7 @@ at least 16 words. == FPGA ============================================================== - wire in_a__; - wire out_r__; - - fifo8x37 fifo8x37(clk, rst, - in_r, in_a__, in_d, - out_r__, out_a, out_d_); - - always @(posedge clk) begin - if (!rst) begin - `reset - end else begin - `flush - out_r <= out_r__; - in_a <= in_a__; - end - end - +// not used == Test ================================================================= // expected output diff --git a/ships/Lut3.ship b/ships/Lut3.ship index dd7831b..7cfd876 100644 --- a/ships/Lut3.ship +++ b/ships/Lut3.ship @@ -78,19 +78,15 @@ is considered ``bit zero''). `reset end else begin `flush - if (!in1_r_ && in1_a) in1_a <= 0; - if (!in2_r_ && in2_a) in2_a <= 0; - if (!in3_r_ && in3_a) in3_a <= 0; - if (!inLut_r_ && inLut_a) inLut_a <= 0; - if (out_r && out_a) begin - in1_a <= 1; - in2_a <= 1; - in3_a <= 1; - inLut_a <= 1; - out_r <= 0; + `cleanup + if (`out_draining) begin + `drain_in1 + `drain_in2 + `drain_in3 + `drain_inLut end - if (in1_r && !in1_a && in2_r && !in2_a && in3_r && !in3_a && inLut_r && !inLut_a && !out_r && !out_a) begin - out_r <= 1; + if (`in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin + `fill_out end end end diff --git a/ships/Memory.ship b/ships/Memory.ship index 29f0888..cb36dd0 100644 --- a/ships/Memory.ship +++ b/ships/Memory.ship @@ -193,44 +193,37 @@ sequence guarantee problem mentioned in the previous paragraph. dispatching_cbd <= 0; end else begin `flush + `cleanup write_flag <= 0; - if (!inAddrRead_r_ && inAddrRead_a) inAddrRead_a <= 0; - if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0; - if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0; - if (!inCBD_r_ && inCBD_a) inCBD_a <= 0; - // assumes we never want a zero-length codebag - if ( inCBD_r && !inCBD_a && !out_r && !out_a) begin + if (`inCBD_full && `out_empty) begin if (!dispatching_cbd) begin cursor <= inCBD_d[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)]; counter <= 0; dispatching_cbd <= 1; end - out_r <= 1; + `fill_out out_w <= 0; - end else if (inCBD_r && out_r && out_a) begin - out_r <= 0; + end else if (`inCBD_full && `out_draining) begin if (counter != inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin cursor <= cursor + 1; counter <= counter + 1; end else begin - inCBD_a <= 1; + `drain_inCBD counter <= 0; dispatching_cbd <= 0; end - end else if (!dispatching_cbd && out_r && out_a) begin out_r <= 0; - end else if (!dispatching_cbd && !out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin - inAddrRead_a <= 1; - out_r <= 1; - out_w <= 0; - - end else if (!dispatching_cbd && !out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin - // timing note: it's okay to set the *_a flags here because *_d will still - // be valid on the *next* cycle, which is all we care about - inAddrWrite_a <= 1; - inDataWrite_a <= 1; - out_r <= 1; + end else if (!dispatching_cbd && `out_empty && `inAddrRead_full) begin + `drain_inAddrRead + `fill_out + + end else if (!dispatching_cbd && `out_empty && `inAddrWrite_full && `inDataWrite_full) begin + // timing note: it's okay to drain here because *_d will still + // be valid on the *very next* cycle, which is all we care about + `drain_inAddrWrite + `drain_inDataWrite + `fill_out write_flag <= 1; out_w <= 1; end diff --git a/ships/Rotator.ship b/ships/Rotator.ship index 0049ab8..e3d7208 100644 --- a/ships/Rotator.ship +++ b/ships/Rotator.ship @@ -36,6 +36,9 @@ public void service() { reg [(`DATAWIDTH):0] out_d; assign out_d_ = out_d; + reg full; + initial full = 0; + reg [5:0] shamt; initial shamt = 0; @@ -45,22 +48,23 @@ public void service() { always @(posedge clk) begin if (!rst) begin `reset + full <= 0; end else begin `flush - if (!in_r_ && in_a && !inAmount_r) in_a <= 0; - if (!inAmount_r_ && inAmount_a) inAmount_a <= 0; - if (out_r && out_a) out_r <= 0; - if (in_r && !in_a && inAmount_r && !inAmount_a && !out_r && !out_a) begin - in_a <= 1; - out_d <= { 1'b0, in_d }; - shamt <= 0; - end else if (in_a && inAmount_r && !inAmount_a && !out_r && !out_a) begin - if (!shamt_eq) begin - out_d <= { out_d[0], out_d[0], out_d[`DATAWIDTH-1:1] }; - shamt <= shamt+1; + `cleanup + if (`in_full && `inAmount_full && `out_empty) begin + if (!full) begin + out_d <= { 1'b0, in_d }; + shamt <= 0; + full <= 1; + end else if (!shamt_eq) begin + out_d <= { out_d[0], out_d[0], out_d[`DATAWIDTH-1:1] }; + shamt <= shamt+1; end else begin - inAmount_a <= 1; - out_r <= 1; + `drain_in + `drain_inAmount + `fill_out + full <= 0; end end end diff --git a/ships/Video.ship b/ships/Video.ship index ec54993..34e0a26 100644 --- a/ships/Video.ship +++ b/ships/Video.ship @@ -93,16 +93,14 @@ data in: inData `reset end else begin `flush + `cleanup vga_pixel_a <= vga_pixel_r; - if (!inData_r_ && inData_a) inData_a <= 0; - if (!inX_r_ && inX_a) inX_a <= 0; - if (!inY_r_ && inY_a) inY_a <= 0; - if (inX_r && !inX_a && inY_r && !inY_a && inData_r && !inData_a) begin + if (`inX_full && `inY_full && `inData_full) begin we <= 1; - inX_a <= 1; - inY_a <= 1; - inData_a <= 1; + `drain_inX + `drain_inY + `drain_inData end else begin we <= 0; end diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java index 2ab89a5..b2cfd92 100644 --- a/src/edu/berkeley/fleet/fpga/Fpga.java +++ b/src/edu/berkeley/fleet/fpga/Fpga.java @@ -92,13 +92,16 @@ public class Fpga extends FleetTwoFleet { this.top = top; debugShip = createShip("Debug", "debug"); - boolean small = false; + //boolean small = false; + boolean small = true; createShip("Memory", "memory1"); if (small) { - createShip("Fifo", "fifo"); - createShip("Alu", "alu"); + for(int i=0; i<2; i++) + createShip("Fifo", "fifo"+i); + for(int i=0; i<2; i++) + createShip("Alu", "alu"+i); createShip("Counter", "counter"); createShip("CarrySaveAdder", "csa1"); createShip("Rotator", "rotator"); @@ -110,10 +113,8 @@ public class Fpga extends FleetTwoFleet { for(int i=0; i<3; i++) createShip("Alu", "alu"+i); - /* - for(int i=0; i<2; i++) + for(int i=0; i<1; i++) createShip("Fifo", "fifo"+i); - */ for(int i=0; i<14; i++) createShip("Counter", "counter"+i); @@ -248,6 +249,13 @@ public class Fpga extends FleetTwoFleet { pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)"); } } + if (debug) { + String name = "out"; + pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)"); + pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)"); + pw.println("`define fill_"+name+" "+name+"_r <= 1;"); + pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)"); + } pw.print("`define reset "); for(DockDescription bb : sd) { @@ -255,8 +263,33 @@ public class Fpga extends FleetTwoFleet { if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; "); else pw.print(bb_name+"_r <= 0; "); } + if (debug) { + String bb_name = "out"; + pw.print(bb_name+"_r <= 0; "); + } pw.println(); + pw.print("`define cleanup "); + for(DockDescription bb : sd) { + String bb_name = bb.getName(); + if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; "); + else pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; "); + } + if (debug) { + String bb_name = "out"; + pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; "); + } + pw.println(); + + // FIXME: this corresponds to something + /* + pw.print("`define flush_happening (1"); + for(DockDescription bb : sd) + if (bb.isInputDock()) + pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a && "+bb.getName()+"_d["+WIDTH_WORD+"]"); + pw.println(")"); + */ + pw.print("`define flush "); for(DockDescription bb : sd) if (bb.isInputDock()) @@ -354,11 +387,6 @@ public class Fpga extends FleetTwoFleet { pw.println(); pw.println(" input clk;"); pw.println(" input rst;"); - if (filename.equals("debug")) { - pw.println(" output ["+WIDTH_WORD+":0] out_d_;"); - pw.println(" input out_a;"); - pw.println(" output out_r_;"); - } if (filename.equals("dram")) { pw.println("output [31:0] dram_addr_;"); pw.println("output dram_addr_r_;"); @@ -421,8 +449,34 @@ public class Fpga extends FleetTwoFleet { } pw.println(); } + if (filename.equals("debug")) { + String bb_name = "out"; + pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;"); + pw.println(" input "+bb_name+"_a;"); + pw.println(" output "+bb_name+"_r_;"); + pw.println(" reg "+bb_name+"_r;"); + pw.println(" initial "+bb_name+"_r = 0;"); + pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;"); + } - pw.println(sd.getSection("fpga")); + if (filename.equals("fifo")) { + pw.println(" wire in_a__;"); + pw.println(" wire out_r__;"); + pw.println(" fifo8x37 fifo8x37(clk, rst,"); + pw.println(" in_r, in_a__, in_d,"); + pw.println(" out_r__, out_a, out_d_);"); + pw.println(" always @(posedge clk) begin"); + pw.println(" if (!rst) begin"); + pw.println(" `reset"); + pw.println(" end else begin"); + pw.println(" `flush"); + pw.println(" out_r <= out_r__;"); + pw.println(" in_a <= in_a__;"); + pw.println(" end"); + pw.println(" end"); + } else { + pw.println(sd.getSection("fpga")); + } pw.println("endmodule"); -- 1.7.10.4