From d01cd280d2dd1415a5f9455f4f4c48e966e28f33 Mon Sep 17 00:00:00 2001 From: adam Date: Sun, 16 Nov 2008 07:48:10 +0100 Subject: [PATCH] percolate ports for vga, ignore ddr2 --- ships/Video.ship | 11 ++++ src/edu/berkeley/fleet/fpga/Fpga.java | 50 --------------- src/edu/berkeley/fleet/fpga/verilog/Verilog.java | 71 ---------------------- 3 files changed, 11 insertions(+), 121 deletions(-) diff --git a/ships/Video.ship b/ships/Video.ship index 34e0a26..03f463c 100644 --- a/ships/Video.ship +++ b/ships/Video.ship @@ -5,6 +5,17 @@ data in: inX data in: inY data in: inData +percolate down: vga_clk 1 +percolate up: vga_psave 1 +percolate up: vga_hsync 1 +percolate up: vga_vsync 1 +percolate up: vga_sync 1 +percolate up: vga_blank 1 +percolate up: vga_r 8 +percolate up: vga_g 8 +percolate up: vga_b 8 +percolate up: vga_clkout 1 + == TeX ============================================================== == Fleeterpreter ==================================================== diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java index 0f751b2..b0aa067 100644 --- a/src/edu/berkeley/fleet/fpga/Fpga.java +++ b/src/edu/berkeley/fleet/fpga/Fpga.java @@ -337,31 +337,6 @@ public class Fpga extends FleetTwoFleet { pw.print(" , "); pw.println(pp.name); } - if (filename.equals("ddr2")) { - pw.println(" , ddr2_addr_"); - pw.println(" , ddr2_addr_r_"); - pw.println(" , ddr2_addr_a"); - pw.println(" , ddr2_isread_"); - pw.println(" , ddr2_write_data_"); - pw.println(" , ddr2_write_data_push_"); - pw.println(" , ddr2_write_data_full"); - pw.println(" , ddr2_read_data"); - pw.println(" , ddr2_read_data_pop_"); - pw.println(" , ddr2_read_data_empty"); - pw.println(" , ddr2_read_data_latency"); - } - if (filename.equals("video")) { - pw.println(" , vga_clk"); - pw.println(" , vga_psave"); - pw.println(" , vga_hsync"); - pw.println(" , vga_vsync"); - pw.println(" , vga_sync"); - pw.println(" , vga_blank"); - pw.println(" , vga_r"); - pw.println(" , vga_g"); - pw.println(" , vga_b"); - pw.println(" , vga_clkout"); - } pw.println(" );"); pw.println(); pw.println(" input clk;"); @@ -375,31 +350,6 @@ public class Fpga extends FleetTwoFleet { pw.print(pp.name); pw.println(";"); } - if (filename.equals("ddr2")) { - pw.println("output [31:0] ddr2_addr_;"); - pw.println("output ddr2_addr_r_;"); - pw.println("input ddr2_addr_a;"); - pw.println("output ddr2_isread_;"); - pw.println("output [63:0] ddr2_write_data_;"); - pw.println("output ddr2_write_data_push_;"); - pw.println("input ddr2_write_data_full;"); - pw.println("input [63:0] ddr2_read_data;"); - pw.println("output ddr2_read_data_pop_;"); - pw.println("input ddr2_read_data_empty;"); - pw.println("input [1:0] ddr2_read_data_latency;"); - } - if (filename.equals("video")) { - pw.println("input vga_clk;"); - pw.println("output vga_psave;"); - pw.println("output vga_hsync;"); - pw.println("output vga_vsync;"); - pw.println("output vga_sync;"); - pw.println("output vga_blank;"); - pw.println("output [7:0] vga_r;"); - pw.println("output [7:0] vga_g;"); - pw.println("output [7:0] vga_b;"); - pw.println("output vga_clkout;"); - } for(DockDescription bb : sd) { String bb_name = bb.getName(); diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java index bbf8c1e..838d823 100644 --- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java +++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java @@ -306,31 +306,6 @@ public class Verilog { pw.println(", " + getPort(s).getSimpleInterface()); for(PercolatedPort pp : module.percolatedPorts) pw.println(" , "+pp.name); - if (module.name.equals("ddr2")) { - pw.println(" , ddr2_addr"); - pw.println(" , ddr2_addr_r"); - pw.println(" , ddr2_addr_a"); - pw.println(" , ddr2_isread"); - pw.println(" , ddr2_write_data"); - pw.println(" , ddr2_write_data_push"); - pw.println(" , ddr2_write_data_full"); - pw.println(" , ddr2_read_data"); - pw.println(" , ddr2_read_data_pop"); - pw.println(" , ddr2_read_data_empty"); - pw.println(" , ddr2_read_data_latency"); - } - if (module.name.equals("video")) { - pw.println(" , vga_clk"); - pw.println(" , vga_psave"); - pw.println(" , vga_hsync"); - pw.println(" , vga_vsync"); - pw.println(" , vga_sync"); - pw.println(" , vga_blank"); - pw.println(" , vga_r"); - pw.println(" , vga_g"); - pw.println(" , vga_b"); - pw.println(" , vga_clkout"); - } pw.println(" );"); } public Port getPort(String name) { @@ -498,29 +473,6 @@ public class Verilog { for (InstantiatedModule im : this.instantiatedModules) for(PercolatedPort pp : im.module.percolatedPorts) pw.println(" , "+pp.name); - if (this.name.equals("root")) { - pw.println(" , vga_clk"); - pw.println(" , vga_psave"); - pw.println(" , vga_hsync"); - pw.println(" , vga_vsync"); - pw.println(" , vga_sync"); - pw.println(" , vga_blank"); - pw.println(" , vga_r"); - pw.println(" , vga_g"); - pw.println(" , vga_b"); - pw.println(" , vga_clkout"); - pw.println(" , ddr2_addr"); - pw.println(" , ddr2_addr_r"); - pw.println(" , ddr2_addr_a"); - pw.println(" , ddr2_isread"); - pw.println(" , ddr2_write_data"); - pw.println(" , ddr2_write_data_push"); - pw.println(" , ddr2_write_data_full"); - pw.println(" , ddr2_read_data"); - pw.println(" , ddr2_read_data_pop"); - pw.println(" , ddr2_read_data_empty"); - pw.println(" , ddr2_read_data_latency"); - } pw.println(" );"); pw.println(); pw.println(" input clk;"); @@ -535,29 +487,6 @@ public class Verilog { pw.print(pp.name); pw.println(";"); } - if (this.name.equals("root")) { - pw.println("output [31:0] ddr2_addr;"); - pw.println("output ddr2_addr_r;"); - pw.println("input ddr2_addr_a;"); - pw.println("output ddr2_isread;"); - pw.println("output [63:0] ddr2_write_data;"); - pw.println("output ddr2_write_data_push;"); - pw.println("input ddr2_write_data_full;"); - pw.println("input [63:0] ddr2_read_data;"); - pw.println("output ddr2_read_data_pop;"); - pw.println("input ddr2_read_data_empty;"); - pw.println("input [1:0] ddr2_read_data_latency;"); - pw.println("input vga_clk;"); - pw.println("output vga_psave;"); - pw.println("output vga_hsync;"); - pw.println("output vga_vsync;"); - pw.println("output vga_sync;"); - pw.println("output vga_blank;"); - pw.println("output [7:0] vga_r;"); - pw.println("output [7:0] vga_g;"); - pw.println("output [7:0] vga_b;"); - pw.println("output vga_clkout;"); - } for(String name : ports.keySet()) { Port p = ports.get(name); pw.println(" " + p.getDeclaration()); -- 1.7.10.4