From d199e884f646ae11853c2c841ffb5753c9d742ae Mon Sep 17 00:00:00 2001 From: adam Date: Mon, 27 Oct 2008 10:15:14 +0100 Subject: [PATCH] move FanoutModule into its own file --- src/edu/berkeley/fleet/fpga/FanoutModule.java | 32 +++++++++++++++++++++++++ src/edu/berkeley/fleet/fpga/FpgaDock.java | 19 --------------- 2 files changed, 32 insertions(+), 19 deletions(-) create mode 100644 src/edu/berkeley/fleet/fpga/FanoutModule.java diff --git a/src/edu/berkeley/fleet/fpga/FanoutModule.java b/src/edu/berkeley/fleet/fpga/FanoutModule.java new file mode 100644 index 0000000..360da16 --- /dev/null +++ b/src/edu/berkeley/fleet/fpga/FanoutModule.java @@ -0,0 +1,32 @@ +package edu.berkeley.fleet.fpga; +import edu.berkeley.fleet.api.*; +import edu.berkeley.fleet.two.*; +import edu.berkeley.fleet.*; +import java.lang.reflect.*; +import edu.berkeley.sbp.chr.*; +import edu.berkeley.sbp.misc.*; +import edu.berkeley.sbp.meta.*; +import edu.berkeley.sbp.util.*; +import java.util.*; +import java.io.*; +import static edu.berkeley.fleet.two.FleetTwoFleet.*; +import static edu.berkeley.fleet.fpga.verilog.Verilog.*; + +public class FanoutModule extends Module { + public FanoutModule(int width) { + super("fanout"+width); + Module.SourcePort in = createInputPort ("in", width); + Module.SinkPort out0 = createOutputPort("out0", width, ""); + Module.SinkPort out1 = createOutputPort("out1", width, ""); + in.hasLatch = false; + out0.hasLatch = false; + out1.hasLatch = false; + addPreCrap("assign out0 = in;"); + addPreCrap("assign out1 = in;"); + addPreCrap("assign out0_r = in_r;"); + addPreCrap("assign out1_r = in_r;"); + addPreCrap("reg in_a__;"); + addPreCrap("assign in_a = in_a__;"); + addPreCrap("always @(posedge clk) begin if (out0_a && out1_a) in_a__ <= 1; if (!out0_a && !out1_a) in_a__ <= 0; end"); + } +} diff --git a/src/edu/berkeley/fleet/fpga/FpgaDock.java b/src/edu/berkeley/fleet/fpga/FpgaDock.java index b466b7a..921bf2c 100644 --- a/src/edu/berkeley/fleet/fpga/FpgaDock.java +++ b/src/edu/berkeley/fleet/fpga/FpgaDock.java @@ -79,25 +79,6 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { } } - public static class FanoutModule extends Module { - public FanoutModule(int width) { - super("fanout"+width); - Module.SourcePort in = createInputPort ("in", width); - Module.SinkPort out0 = createOutputPort("out0", width, ""); - Module.SinkPort out1 = createOutputPort("out1", width, ""); - in.hasLatch = false; - out0.hasLatch = false; - out1.hasLatch = false; - addPreCrap("assign out0 = in;"); - addPreCrap("assign out1 = in;"); - addPreCrap("assign out0_r = in_r;"); - addPreCrap("assign out1_r = in_r;"); - addPreCrap("reg in_a__;"); - addPreCrap("assign in_a = in_a__;"); - addPreCrap("always @(posedge clk) begin if (out0_a && out1_a) in_a__ <= 1; if (!out0_a && !out1_a) in_a__ <= 0; end"); - } - } - public static class RequeueModule extends Module { public RequeueModule() { super("requeue"); -- 1.7.10.4