From d880743076f26614db870469e0c66c5eb520d7dd Mon Sep 17 00:00:00 2001 From: megacz Date: Mon, 29 Dec 2008 17:42:00 -0800 Subject: [PATCH] eliminate use of the `XXX_draining macro --- ships/Alu.ship | 9 +++++++-- ships/Counter.ship | 10 +++++++--- ships/Lut3.ship | 8 ++++++-- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/ships/Alu.ship b/ships/Alu.ship index 3b2117f..fa9dfd8 100644 --- a/ships/Alu.ship +++ b/ships/Alu.ship @@ -143,6 +143,8 @@ public void service() { assign eq = in1_d == in2_d; assign cout = sum[`WORDWIDTH]; + reg out_draining; + assign out_d_[`WORDWIDTH] = (inOp_d_trunc==0) ? 1'b0 : (inOp_d_trunc==1) ? 1'b0 : @@ -168,11 +170,13 @@ public void service() { always @(posedge clk) begin if (!rst) begin `reset + out_draining <= 0; end else begin `flush `cleanup - if (`out_draining) begin + if (out_draining && `out_empty) begin `drain_inOp + out_draining <= 0; if (inOp_d_trunc==0) `drain_in1 else if (inOp_d_trunc==1) `drain_in2 else if (inOp_d_trunc==9 && both_negative) begin `drain_in1 `drain_in2 end @@ -187,8 +191,9 @@ public void service() { `drain_in2 end end - if (`out_empty && `in1_full && `in2_full && `inOp_full) begin + if (!out_draining && `out_empty && `in1_full && `in2_full && `inOp_full) begin `fill_out + out_draining <= 1; end end end diff --git a/ships/Counter.ship b/ships/Counter.ship index 2e71152..f82bc14 100644 --- a/ships/Counter.ship +++ b/ships/Counter.ship @@ -31,6 +31,7 @@ public void service() { } reg [`WORDWIDTH-1:0] temp; initial temp = {`WORDWIDTH{1'b1}}; + reg out_draining; reg full; initial full = 0; wire op_count; assign op_count = inOp_d_trunc==12; @@ -49,15 +50,17 @@ public void service() { } if (!rst) begin `reset full <= 0; + out_draining <= 0; end else begin `flush `cleanup if (`inOp_empty) full <= 0; - if (`out_draining) begin + if (out_draining && `out_empty) begin if (op_count) temp <= temp - in2_d; else temp <= temp - 1; if (op_pass && op_v1) `drain_in1 if (op_pass && op_v2) `drain_in2 + out_draining <= 0; end else if (`inOp_full) begin if (!full) begin if (op_count && `in1_full && `in2_full) begin @@ -86,12 +89,13 @@ public void service() { } end else if (`out_empty) begin if (op_count) begin `fill_out + out_draining <= 1; end else if (op_v1 && `in1_full) begin if (op_drop) begin `drain_in1 temp <= temp-1; end - else `fill_out + else begin `fill_out out_draining <= 1; end end else if (op_v2 && `in2_full) begin if (op_drop) begin `drain_in2 temp <= temp-1; end - else `fill_out + else begin `fill_out out_draining <= 1; end end end end diff --git a/ships/Lut3.ship b/ships/Lut3.ship index e6bd469..4c8401e 100644 --- a/ships/Lut3.ship +++ b/ships/Lut3.ship @@ -62,6 +62,7 @@ is considered ``bit zero''). == FleetSim ============================================================== == FPGA ============================================================== + reg out_draining; wire [7:0] lut; genvar i; @@ -76,17 +77,20 @@ is considered ``bit zero''). always @(posedge clk) begin if (!rst) begin `reset + out_draining <= 0; end else begin `flush `cleanup - if (`out_draining) begin + if (out_draining && `out_empty) begin `drain_in1 `drain_in2 `drain_in3 `drain_inLut + out_draining <= 0; end - if (`in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin + if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin `fill_out + out_draining <= 1; end end end -- 1.7.10.4