From ea6b1155539acf27cf60cce59602ff93dff6131d Mon Sep 17 00:00:00 2001 From: adam Date: Mon, 10 Nov 2008 15:03:45 +0100 Subject: [PATCH] clean up top-level module logic a bit --- src/edu/berkeley/fleet/fpga/Fpga.java | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java index 65f9953..9afdcc6 100644 --- a/src/edu/berkeley/fleet/fpga/Fpga.java +++ b/src/edu/berkeley/fleet/fpga/Fpga.java @@ -158,7 +158,6 @@ public class Fpga extends FleetTwoFleet { numdocks++; } } - //System.err.println("dock count = " + numdocks); ArrayList dests = new ArrayList(); ArrayList sources = new ArrayList(); sources.addAll(inbox_sources); @@ -170,27 +169,24 @@ public class Fpga extends FleetTwoFleet { FabricElement source = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false); FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort()); ((FunnelModule.FunnelInstance)source).out = top_funnel; - //top_horn.addInput(top_funnel, top_funnel.getOutputPort()); top_funnel.addOutput(top_horn, top_horn.getInputPort()); - - //Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET); Module.SinkPort debug_in = top_funnel.getInputPort("in1"); top.new Event(new Object[] { in, "count<=7" }, new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"), - new SimpleAction("count <= count+1;"), + new AssignAction(count, count.getVerilogName()+"+1"), in }); top.new Event(new Object[] { debug_in, "count>7" }, - new Object[] { new SimpleAction(" count <= 0; "), + new Object[] { new AssignAction(count, "0"), new AssignAction(debug_in, temp_in), debug_in }); top.new Event(new Object[] { out, debug_out }, new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"), - new SimpleAction("if (count_out >= 5) begin "+ - "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+ - " else count_out <= count_out+1; "), + new ConditionalAction("count_out >= 5", debug_out), + new ConditionalAction("count_out >= 5", new AssignAction(count_out, "0")), + new ConditionalAction("count_out < 5", new AssignAction(count_out, "count_out+1")), out }); } -- 1.7.10.4