merge proof correction

[coq-hetmet.git] / examples / Makefile

diff --git a/examples/Makefile b/examples/Makefile
index ff6f713..4e47c6e 100644 (file)
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -1,11 +1,15 @@
-ghc_opt := -fwarn-incomplete-patterns -Werror -odir .build -hidir .build
+# -fwarn-incomplete-patterns
+
+ghc = ../../../inplace/bin/ghc-stage2
+#ghc = ghc
+ghc_opt :=  -Werror -odir .build -hidir .build
 
 open:
        make demo
        open .build/test.pdf
 
 #sanity += BiGArrow.hs
-sanity += KappaDemo.hs
+sanity += IFLDemos.hs
 sanity += CircuitExample.hs
 sanity += CommandSyntaxExample.hs
 sanity += DotProduct.hs
@@ -22,13 +26,24 @@ sanity_opts += -fsimpleopt-before-flatten
 sanity_opts += -odir .build -hidir .build 
 
 sanity:
-       for A in $(sanity); do echo; echo; ../../../inplace/bin/ghc-stage2 $(sanity_opts) $$A +RTS -K500M || exit -1; done
+       for A in $(sanity); do echo; echo; $(ghc) $(sanity_opts) $$A +RTS -K500M || exit -1; done
+
+demo-pretty:
+       $(ghc) $(ghc_opt) -main-is GArrowPretty GArrowPretty.hs -o GArrowPretty
+
+demo-v:
+       $(ghc) $(ghc_opt) -main-is GArrowVerilog GArrowVerilog.hs -o GArrowVerilog
+       ./GArrowVerilog
 
+demo-verilog:
+       $(ghc) $(sanity_opts) -c VerilogDemo.hs
+       $(ghc) $(ghc_opt) -main-is GArrowVerilog GArrowVerilog.hs -o GArrowVerilog
+       ./GArrowVerilog
 
 demo:
        mkdir -p .build
-       ../../../inplace/bin/ghc-stage2 $(ghc_opt) -c Demo.hs -fforce-recomp
-       ../../../inplace/bin/ghc-stage2 $(ghc_opt) --show-iface .build/Demo.hi
-       ../../../inplace/bin/ghc-stage2 $(ghc_opt) GArrowTikZ.hs Demo.hs DemoMain.hs Unify.hs -o .build/demo
+       $(ghc) $(ghc_opt) -c Demo.hs -fforce-recomp
+       $(ghc) $(ghc_opt) --show-iface .build/Demo.hi
+       $(ghc) $(ghc_opt) GArrowTikZ.hs Demo.hs DemoMain.hs Unify.hs -o .build/demo
        ./.build/demo > .build/test.tex
        cd .build; TEXINPUTS=../tex-bits/:$TEXINPUTS: pdflatex test.tex