rewrite GArrowVerilog

[coq-hetmet.git] / examples / Makefile

diff --git a/examples/Makefile b/examples/Makefile
index 7926143..ff6f713 100644 (file)
--- a/examples/Makefile
+++ b/examples/Makefile
@@ -1,10 +1,11 @@
-ghc_opt := -fwarn-incomplete-patterns -Werror -odir .build -hidir .build 
+ghc_opt := -fwarn-incomplete-patterns -Werror -odir .build -hidir .build
 
 open:
        make demo
        open .build/test.pdf
 
 #sanity += BiGArrow.hs
+sanity += KappaDemo.hs
 sanity += CircuitExample.hs
 sanity += CommandSyntaxExample.hs
 sanity += DotProduct.hs
@@ -30,4 +31,4 @@ demo:
        ../../../inplace/bin/ghc-stage2 $(ghc_opt) --show-iface .build/Demo.hi
        ../../../inplace/bin/ghc-stage2 $(ghc_opt) GArrowTikZ.hs Demo.hs DemoMain.hs Unify.hs -o .build/demo
        ./.build/demo > .build/test.tex
-       cd .build; pdflatex test.tex
+       cd .build; TEXINPUTS=../tex-bits/:$TEXINPUTS: pdflatex test.tex