projectname = working-bee2 build_machine = sting.eecs.berkeley.edu build_machine_xilinx_path = /opt/xilinx/ISE9.2i_lin/ build_machine_work_dir = ~/$(projectname) bee2_machine = board4 ## you probably want to customize the stuff above this line ## you probably don't want to change anything below this line xilinx = cd $(build_machine_work_dir); xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin xilinx += XILINX=$(XILINX) xilinx += PATH=$$PATH:$(XILINX)/bin/lin xilinx += $(XILINX)/bin/lin/ bitfile = map0.bit remote_run = user_unprogram 1; remote_run += user_program 1 $(bitfile); verilog_files = $(find . -name \*.v) run: upload build/fpga/$(bitfile) ssh root@$(bee2_machine) '$(remote_run)' upload: build/fpga/$(bitfile) scp build/fpga/$(bitfile) root@$(bee2_machine): build/fpga/$(bitfile): $(verilog_files) mkdir -p build/fpga/ rsync -zare --progress --delete --verbose ./ ${build_machine_work_dir} time ssh ${build_machine} 'make -C ${build_machine_work_dir} -f Makefile0 synth XILINX=${build_machine_xilinx_path}' cp main.bit build/fpga/$(bitfile) synth: mkdir -p build/fpga/ echo work > main.lso for A in *.v; do echo verilog work \""$$A"\"; done > main.prj mkdir -p tmp mkdir -p xst rm -rf build/fpga/_ngo $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd # $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf