Author: Tracy Wang

Everything in this folder is the framework that I used to test the interchip on the Bee2. 

Here's a short list of important files and their description.

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main.v

This is the *generic* top level verilog file which hooks up the selectmap FIFOs (async_fifo_* files). Then it hooks the FIFOs to the testing file, in this case in root.v. Actual test resides in root.v. 

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main_counterexample_map0

This is the main file which hooks up the counterexample Map0. So it hooks up the selectmap to BTN and SW. It also connects the interchip terminal to the right pins on Bee2.

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main_counterexample_map1

This is the main file which hooks up the counterexample Map1. It connects the counter outputs to the selectmap FIFO. 

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Makefile_userfpga

This is the *generic* makefile which can be invoked from the control fpga to program the testing harness automatically onto one of the user fpgas. However, it will prompt for password in several locations, which I wasn't able to bypass.

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makemaps.pl

This is the perl file which I used to invoke Makefile_interchip0 and Makefile interchip1 to build the two interchip maps. This file requires customization of the Makefile file names.
Both Makefile_interchip0 and Makefile_interchip1 will program the bit files onto the boards. Makefile_interchip1 will actually run a remote_run.pl file after everything is programmed to automatically test the unit and retrieve the results.

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How to use selectmap

To input characters into selectmap:

echo "<characters here>" > /dev/selectmap[1-4];

To read from selectmap

head -c<number of characters> /dev/selectmap[1-4];

i.e. if I'm on board 2, and I program a single unit which counts every time I receive a character from the selectmap, I would do the following

echo "12345" > /dev/selectmap2;
head -c5 /dev/selectmap2;

i.e. if I'm on board1, and the interchip connects to board2, I would do something like 

echo "12345" > /dev/selectmap1;
head -c5 /dev/selectmap2;

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Finally, step by step instructions on how to go from a verilog project to programming it and running it on the Bee2.

1. Use RDLC to generate files from the RDL
2. Copy all verilog files into a single flat directory on a server connected to a bee2 board (like sting)
3. Make sure the selectmap FIFO, main*.v and Makefile* are also in that same directory.
4. Customize the main*.v files to connect the right ports to selectmap FIFOs, and your Maps. If you have multiple Maps, make two separate main files
5. Customize the Makefile to point to the right chip. If you are making two maps, make two Makefiles.
6. Run Makefile. The original Makefiles will program the chips automatically.
7. Use the above instructions to start running the tests by echoing characters into the selectmap.