ship: Alu == Ports =========================================================== data in: in1 data in: in2 data in: inOp constant IN1: 0 constant IN2: 1 constant ADD: 2 constant SUB: 3 constant MAX: 4 constant MIN: 5 constant CMP: 6 constant DROP1: 7 constant DROP2: 8 constant MAXMERGE: 9 data out: out == TeX ============================================================== {\tt Alu} is a ``two-input'' arithmetic logic unit. It includes logic for performing arithmetic operations on a pair of arguments. Currently this includes addition ({\sc add}), subtraction ({\sc sub}), maximum ({\sc max}), and minimum ({\sc min}). \subsection*{Semantics} When a value is present at each of {\tt in1}, {\tt in2} and {\tt inOp}, these three values are consumed. Based on the value consumed at {\tt inOp}, the requested operation is performed on the values consumed from {\tt in1} and {\tt in2}. The result of this operation is then made available at {\tt out}. \subsection*{C-Flag} \begin{verbatim} IN1 - undefined; drain in1 only IN2 - undefined; drain in2 only ADD - carry-out SUB - undefined MAX - if in1>in2 cflag=0 and drain in1, else cflag=1 and drain in2 MIN - if in1>in2 cflag=1 and drain in2, else cflag=0 and drain in1 CMP - if in1==in2 cflag=1, else cflag=0 DROP1 - consume in1, produce no output DROP2 - consume in2, produce no output MAXMERGE - if (in1<0 && in2<0) consume both, emit either, cflag=undef else act as MAX \end{verbatim} \subsection*{To Do} The {\it link bit} and other features of \cite{ies31} are not yet implemented. The carry-in, carry-out, zero-test, negative-test, and overflow-test flags typically present in a conventional processor ALU are also not yet implemented. == Fleeterpreter ==================================================== public void service() { if (box_inOp.dataReadyForShip() && box_in1.dataReadyForShip() && box_in2.dataReadyForShip() && box_out.readyForDataFromShip()) { long a; long b; long op = box_inOp.removeDataForShip(); switch((int)op) { case 0: a = box_in1.removeDataForShip(); box_out.addDataFromShip(a); // IN1 break; case 1: b = box_in2.removeDataForShip(); box_out.addDataFromShip(b); // IN2 break; case 2: a = box_in1.removeDataForShip(); b = box_in2.removeDataForShip(); box_out.addDataFromShip(a+b); // ADD break; case 3: a = box_in1.removeDataForShip(); b = box_in2.removeDataForShip(); box_out.addDataFromShip(a-b); // SUB break; case 4: a = box_in1.peekDataForShip(); b = box_in2.peekDataForShip(); box_out.addDataFromShip(Math.max(a,b)); // MAX box_out.flag_c = !(a>b); if (ab; if (a>b) box_in1.removeDataForShip(); else box_in2.removeDataForShip(); break; case 6: a = box_in1.removeDataForShip(); b = box_in2.removeDataForShip(); box_out.addDataFromShip(0); // CMP box_out.flag_c = a==b; break; default: a = box_in1.removeDataForShip(); b = box_in2.removeDataForShip(); box_out.addDataFromShip(0); break; } } } == FleetSim ============================================================== == FPGA ============================================================== wire [`WORDWIDTH:0] sum; wire cin; wire [(`WORDWIDTH-1):0] in2_inverted; wire [(`WORDWIDTH-1):0] res; wire isplus; wire eq; wire cout; assign isplus = inOp_d[2:0]==2; assign cin = isplus ? 0 : 1; assign in2_inverted = isplus ? in2_d : ~in2_d; assign sum = {in1_d,cin} + {in2_inverted,cin}; assign res = sum[`WORDWIDTH:1]; assign greater = !res[`WORDWIDTH-1]; assign both_negative = in1_d[`WORDWIDTH-1] && in2_d[`WORDWIDTH-1]; assign eq = in1_d == in2_d; assign cout = sum[`WORDWIDTH]; assign out_d_[`WORDWIDTH] = (inOp_d==0) ? 1'b0 : (inOp_d==1) ? 1'b0 : (inOp_d==2) ? cout : (inOp_d==3) ? cout : (inOp_d==4) ? ~greater : (inOp_d==5) ? greater : (inOp_d==6) ? eq : (inOp_d==9) ? ~greater : 0; assign out_d_[(`WORDWIDTH-1):0] = (inOp_d==0) ? (in1_d) : (inOp_d==1) ? (in2_d) : (inOp_d==2) ? (res) : (inOp_d==3) ? (res) : (inOp_d==4) ? (greater ? in1_d : in2_d) : (inOp_d==5) ? (greater ? in2_d : in1_d) : (inOp_d==6) ? {{ (`WORDWIDTH-1) {1'b0 }}, eq } : (inOp_d==9) ? (both_negative ? in1_d : (greater ? in1_d : in2_d)) : 0; always @(posedge clk) begin if (!rst) begin `reset end else begin `flush `cleanup if (`out_draining) begin `drain_inOp if (inOp_d==0) `drain_in1 else if (inOp_d==1) `drain_in2 else if (inOp_d==9 && both_negative) begin `drain_in1 `drain_in2 end else if (inOp_d==4 && greater) `drain_in1 else if (inOp_d==5 && greater) `drain_in2 else if (inOp_d==9 && greater) `drain_in1 else if (inOp_d==4 && !greater) `drain_in2 else if (inOp_d==5 && !greater) `drain_in1 else if (inOp_d==9 && !greater) `drain_in2 else begin `drain_in1 `drain_in2 end end if (`out_empty && `in1_full && `in2_full && `inOp_full) begin `fill_out end end end == Test ============================================================================== // FIXME: need test for ADD carry-out c-flag #ship debug : Debug #ship alu : Alu #expect 17 #expect 1 #expect 9 #expect 8 #expect 8 #expect 1 #expect 9 #expect 0 #expect 0 #expect 1 debug.in: set ilc=*; recv, deliver; alu.in1: set word= 9; set ilc=5; deliver; set word= 9; deliver; alu.in2: set word= 8; set ilc=5; deliver; set word= 9; deliver; alu.out: set ilc=4; collect, send to debug.in; alu.inOp: set word= Alu.inOp[ADD]; deliver; set word= Alu.inOp[SUB]; deliver; set word= Alu.inOp[IN1]; deliver; set word= Alu.inOp[IN2]; deliver; set word= Alu.inOp[MIN]; deliver; set word= Alu.inOp[MAX]; deliver; set word= Alu.inOp[CMP]; deliver; set word= Alu.inOp[CMP]; deliver; alu.out: collect, send to debug.in; // MIN set flags a=c, b=b; [a] set word= 1; [!a] set word= 0; send to debug.in; collect, send to debug.in; // MAX set flags a=c, b=b; [a] set word= 1; [!a] set word= 0; send to debug.in; collect; // CMP set flags a=c, b=b; [a] set word= 1; [!a] set word= 0; send to debug.in; collect; // CMP set flags a=c, b=b; [a] set word= 1; [!a] set word= 0; send to debug.in; == Contributors ========================================================= Adam Megacz