ship: DDR2 == Ports =========================================================== data in: inAddrRead data in: inAddrWrite data in: inDataWrite data out: out percolate up: gpio_led_0 1 percolate up: gpio_led_1 1 percolate up: gpio_led_2 1 percolate up: gpio_led_3 1 percolate inout: ddr2_dq 64 percolate up: ddr2_a 13 percolate up: ddr2_ba 2 percolate up: ddr2_ras_n 1 percolate up: ddr2_cas_n 1 percolate up: ddr2_we_n 1 percolate up: ddr2_cs_n 1 percolate up: ddr2_odt 1 percolate up: ddr2_cke 1 percolate up: ddr2_dm 8 percolate up: phy_init_done 1 percolate inout: ddr2_dqs 8 percolate inout: ddr2_dqs_n 8 percolate up: ddr2_ck 2 percolate up: ddr2_ck_n 2 == TeX ============================================================== == Fleeterpreter ==================================================== public void service() { } == FleetSim ============================================================== == FPGA ============================================================== /* percolate inout: ddr2_dq 8 percolate up: ddr2_a 15 percolate up: ddr2_ba 3 percolate up: ddr2_ras_n 1 percolate up: ddr2_cas_n 1 percolate up: ddr2_we_n 1 percolate up: ddr2_cs_n 1 percolate up: ddr2_odt 1 percolate up: ddr2_cke 1 percolate up: ddr2_dm 1 percolate up: phy_init_done 1 percolate inout: ddr2_dqs 1 percolate inout: ddr2_dqs_n 1 percolate up: ddr2_ck 1 percolate up: ddr2_ck_n 1 */ //NET "sys_clk_p" LOC = "H17" ; #Bank 3 //NET "sys_clk_n" LOC = "H18" ; #Bank 3 //NET "clk200_p" LOC = "K17" ; #Bank 3 //NET "clk200_n" LOC = "L18" ; #Bank 3 //NET "sys_rst_n" LOC = "L24" ; #Bank 19 /******************************************************************************* * This file is owned and controlled by Xilinx and must be used * * solely for design, simulation, implementation and creation of * * design files limited to Xilinx devices or technologies. Use * * with non-Xilinx devices or technologies is expressly prohibited * * and immediately terminates your license. * * * * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * * SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * * XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * * AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * * OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * * IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * * FOR A PARTICULAR PURPOSE. * * * * Xilinx products are not intended for use in life support * * appliances, devices, or systems. Use in such applications are * * expressly prohibited. * * * * (c) Copyright 1995-2006 Xilinx, Inc. * * All rights reserved. * *******************************************************************************/ // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG wire clk200_p; wire clk200_n; wire clk_rebuffered; ddr2_sdram # ( .BANK_WIDTH(2), // # of memory bank addr bits. .CKE_WIDTH(1), // # of memory clock enable outputs. .CLK_WIDTH(2), // # of clock outputs. .COL_WIDTH(10), // # of memory column bits. .CS_NUM(1), // # of separate memory chip selects. .CS_WIDTH(1), // # of total memory chip selects. .CS_BITS(0), // set to log2(CS_NUM) (rounded up). .DM_WIDTH(8), // # of data mask bits. .DQ_WIDTH(64), // # of data width. .DQ_PER_DQS(8), // # of DQ data bits per strobe. .DQS_WIDTH(8), // # of DQS strobes. .DQ_BITS(6), // set to log2(DQS_WIDTH*DQ_PER_DQS). .DQS_BITS(3), // set to log2(DQS_WIDTH). .ODT_WIDTH(1), // # of memory on-die term enables. .ROW_WIDTH(13), // # of memory row and # of addr bits. .ADDITIVE_LAT(0), // additive write latency. .BURST_LEN(4), // burst length (in double words). .BURST_TYPE(0), // burst type (=0 seq; =1 interleaved). .CAS_LAT(4), // CAS latency. .ECC_ENABLE(0), // enable ECC (=1 enable). .APPDATA_WIDTH(128), // # of usr read/write data bus bits. .MULTI_BANK_EN(1), // Keeps multiple banks open. (= 1 enable). .TWO_T_TIME_EN(1), // 2t timing for unbuffered dimms. .ODT_TYPE(1), // ODT (=0(none),=1(75),=2(150),=3(50)). .REDUCE_DRV(0), // reduced strength mem I/O (=1 yes). .REG_ENABLE(0), // registered addr/ctrl (=1 yes). .TREFI_NS(7800), // auto refresh interval (ns). .TRAS(40000), // active->precharge delay. .TRCD(15000), // active->read/write delay. .TRFC(127500), // refresh->refresh, refresh->active delay. .TRP(15000), // precharge->command delay. .TRTP(7500), // read->precharge delay. .TWR(15000), // used to determine write->precharge. .TWTR(7500), // write->read delay. .HIGH_PERFORMANCE_MODE("TRUE"), // # = TRUE, the IODELAY performance mode is set to high. // # = FALSE, the IODELAY performance mode is set to low. .SIM_ONLY(0), // = 1 to skip SDRAM power up delay. .DEBUG_EN(0), // Enable debug signals/controls. // When this parameter is changed from 0 to 1, // make sure to uncomment the coregen commands // in ise_flow.bat or create_ise.bat files in // par folder. .CLK_PERIOD(5000), // Core/Memory clock period (in ps). .DQS_IO_COL(16'b0000000000000000), // I/O column location of DQS groups // (=0, left; =1 center, =2 right). //.DQ_IO_MS(64'b10100101_10100101_10100101_10100101_10100101_10100101_10100101_10100101), .DQ_IO_MS(64'b01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100), // Master/Slave location of DQ I/O (=0 slave). .CLK_TYPE("SINGLE_ENDED"), // # = "DIFFERENTIAL " ->; Differential input clocks , // # = "SINGLE_ENDED" -> Single ended input clocks. .DLL_FREQ_MODE("HIGH"), // DCM Frequency range. .RST_ACT_LOW(1) // =1 for active low reset, =0 for active high. ) ddr2_sdram ( .sys_clk (clk), .idly_clk_200 (clk200_p), .sys_rst_n (!rst), .ddr2_dq (ddr2_dq), .ddr2_a (ddr2_a), .ddr2_ba (ddr2_ba), .ddr2_ras_n (ddr2_ras_n), .ddr2_cas_n (ddr2_cas_n), .ddr2_we_n (ddr2_we_n), .ddr2_cs_n (ddr2_cs_n), .ddr2_odt (ddr2_odt), .ddr2_cke (ddr2_cke), .ddr2_dm (ddr2_dm), .ddr2_dqs (ddr2_dqs), .ddr2_dqs_n (ddr2_dqs_n), .ddr2_ck (ddr2_ck), .ddr2_ck_n (ddr2_ck_n), .phy_init_done (gpio_led_0), .app_wdf_afull (gpio_led_1), .app_af_afull (gpio_led_2), .rd_data_valid (gpio_led_3), .app_wdf_wren (1'b1), .app_af_wren (app_af_wren), .app_af_addr (app_af_addr), .app_af_cmd (app_af_cmd), .rd_data_fifo_out (rd_data_fifo_out), .app_wdf_data (app_wdf_data), .app_wdf_mask_data (app_wdf_mask_data) ); wire clk200_p_fb; DCM // 200Mhz DDR clock #( .CLKFX_MULTIPLY(2), .CLKFX_DIVIDE(1), .CLKIN_PERIOD("10 ns") ) vgadcm ( .CLKIN (clk), .CLKFB (clk200_p_fb), .CLKFX (clk200_n), .CLKFX180 (clk200_p), .CLK0 (clk200_p_fb) ); /* always @(posedge clk) begin if (rst) begin `reset CommandValid <= 0; DataOutReady <= 0; end else begin `cleanup CommandValid <= 0; DataInValid <= 0; if (`out_empty) begin DataOutReady <= 1; end if (DataOutReady && DataOutValid && `out_empty) begin out_d <= { 1'b0, DataOut[`WORDWIDTH-1:0] }; `fill_out DataOutReady <= 0; end else if (DataOutReady && CommandReady && DataInReady && `out_empty) begin if (`inAddrWrite_full && `inDataWrite_full) begin `drain_inDataWrite `drain_inAddrWrite CommandAddress <= inAddrWrite_d; Command <= 3'b000; CommandValid <= 1; DataInValid <= 1; out_d <= { 1'b1, 37'b0 }; `fill_out DataOutReady <= 0; end else if (`inAddrRead_full) begin `drain_inAddrRead CommandAddress <= inAddrRead_d; CommandValid <= 1; Command <= 3'b001; DataInValid <= 0; DataOutReady <= 1; end end end end */ == Test ============================================================== #skip #expect 0 #ship debug : Debug #ship ddr : DDR2 debug.in: recv, deliver; ddr.out: collect; set flags a=!c,b=b; send to debug.in; collect; set flags a=!c,b=b; send to debug.in; ddr.inAddrWrite: set word=0; deliver; deliver; ddr.inDataWrite: set word=1; deliver; deliver; == Constants ======================================================== == Contributors ========================================================= Adam Megacz