ship: DRAM

== Ports ===========================================================
data  in:    inAddrRead
data  in:    inAddrWrite
data  in:    inDataWrite

data  out:   out

percolate up:            ddr1_Clk_pin       1
percolate up:            ddr1_Clk_n_pin     1
percolate up:            ddr1_Addr_pin      13
percolate up:            ddr1_BankAddr_pin  2
percolate up:            ddr1_CAS_n_pin     1
percolate up:            ddr1_CE_pin        1
percolate up:            ddr1_CS_n_pin      1
percolate up:            ddr1_RAS_n_pin     1
percolate up:            ddr1_WE_n_pin      1
percolate up:            ddr1_DM_pin        4
percolate inout:         ddr1_DQS           4
percolate inout:         ddr1_DQ            32

== TeX ==============================================================

== Fleeterpreter ====================================================
    public void service() { }
== FleetSim ==============================================================

== FPGA ==============================================================

  wire  [31:0]  dram_addr;
  wire          dram_addr_r_;
  wire          dram_addr_a;
  wire          dram_isread_;
  wire  [63:0]  dram_write_data_;
  wire          dram_write_data_push_;
  wire          dram_write_data_full;
  wire   [63:0] dram_read_data;
  wire          dram_read_data_pop_;
  wire          dram_read_data_empty;
  wire   [1:0]  dram_read_data_latency;

  reg         dram_addr_r;
  reg         dram_isread;
  reg         dram_write_data_push;
  reg         dram_read_data_pop;
  reg  [`WORDWIDTH:0]  out_d;
  wire [31:0] dram_addr__;

  assign dram_addr_r_ = dram_addr_r;
  assign dram_isread_ = dram_isread;
  assign dram_addr__ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
  assign dram_addr_  = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
  assign dram_write_data_push_ = dram_write_data_push;
  assign dram_read_data_pop_ = dram_read_data_pop;
  assign dram_write_data_ = inDataWrite_d;
  assign out_d_ = out_d;

   ddr_ctrl 
   #(
   	.clk_freq( 50000000 ),
   	.clk_multiply( 12 ),
   	.clk_divide( 5 ),
   	.phase_shift( 0 ),
   	.wait200_init( 26 )
   ) ddr_ctrl (
          .ddr_a( ddr1_Addr_pin ),
          .ddr_clk( ddr1_Clk_pin ),
          .ddr_clk_n( ddr1_Clk_n_pin ),
          .ddr_ba( ddr1_BankAddr_pin ),
          .ddr_dq( ddr1_DQ ),
          .ddr_dm( ddr1_DM_pin ),
          .ddr_dqs( ddr1_DQS ),
          .ddr_cs_n( ddr1_CS_n_pin ),
          .ddr_ras_n( ddr1_RAS_n_pin ),
          .ddr_cas_n( ddr1_CAS_n_pin ),
          .ddr_we_n( ddr1_WE_n_pin ),
          .ddr_cke( ddr1_CE_pin ),
   
          .clk(clk),
          .reset(!sys_rst_pin),
          .rot(3'b100),
   
          .fml_wr(!dram_isread && dram_addr_r),
          .fml_done(dram_addr_a),
          .fml_rd( dram_isread && dram_addr_r),
          .fml_adr(dram_addr),
          .fml_din(dram_write_data),
          .fml_dout(dram_read_data),
          .fml_msk(16'h0)
   );

  always @(posedge clk) begin

    if (!rst) begin
      `reset
      dram_isread <= 0;
      dram_addr_r <= 0;
      dram_read_data_pop <= 0;

    end else begin
      `flush
      `cleanup

      if (dram_addr_r && !dram_addr_a) begin
         // busy
      end else if (dram_addr_r &&  dram_addr_a && !dram_isread) begin
          dram_addr_r <= 0;
          `drain_inDataWrite
          `drain_inAddrWrite
          `fill_out
          out_d <= { 1'b1, 37'b0 };
      end else if (dram_addr_r &&  dram_addr_a && dram_isread) begin
          dram_addr_r <= 0;
          `drain_inAddrRead
          `fill_out
          out_d <= { 1'b0, dram_read_data[36:0] };
      end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full && !dram_addr_r && !dram_addr_a) begin
          dram_addr_r <= 1;
          dram_isread <= 0;
      end else if (`out_empty && `inAddrRead_full && !dram_addr_r && !dram_addr_a) begin
          dram_addr_r <= 1;
          dram_isread <= 1;
      end
    end
  end


== Test ========================================================
#skip

== Constants ========================================================

== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>