ship: Lut3 == Ports =========================================================== data in: in1 data in: in2 data in: in3 data in: inLut data out: out == Constants ======================================================== AND OR XOR NAND NOR == TeX ============================================================== This ship implements a bitwise 3-input {\bf L}ook {\bf U}p {\bf T}able. The least significant eight bits of the {\tt inLut} value form a truth table with three inputs and one output. When values are available at all four inputs they are consumed and a value is produced at {\tt out}. Each bit of {\tt out} is produced by looking up the corresponding bits of {\tt in1}, {\tt in2}, and {\tt in3} in the {\tt inLut} truth table. In particular, the bits {\tt in1}, {\tt in2}, {\tt in3} are concatenated to form a three-bit number, with {\tt in3} as the {\it most significant} bit and {\tt in1} as the {\it least significant bit}. This three-bit number, ranging from 0 to 7 (decimal), is used as a bit index into {\tt inLut}'s value (whose least significant bit is considered ``bit zero''). == Fleeterpreter ==================================================== public void service() { if (box_in1.dataReadyForShip() && box_in2.dataReadyForShip() && box_in3.dataReadyForShip() && box_inLut.dataReadyForShip() && box_out.readyForDataFromShip()) { long a = box_in1.removeDataForShip(); long b = box_in2.removeDataForShip(); long c = box_in3.removeDataForShip(); long lut = box_inLut.removeDataForShip(); long ret = 0; ret |= ((lut & (1<<0))==0) ? 0 : (~a) & (~b) & (~c); ret |= ((lut & (1<<1))==0) ? 0 : ( a) & (~b) & (~c); ret |= ((lut & (1<<2))==0) ? 0 : (~a) & ( b) & (~c); ret |= ((lut & (1<<3))==0) ? 0 : ( a) & ( b) & (~c); ret |= ((lut & (1<<4))==0) ? 0 : (~a) & (~b) & ( c); ret |= ((lut & (1<<5))==0) ? 0 : ( a) & (~b) & ( c); ret |= ((lut & (1<<6))==0) ? 0 : (~a) & ( b) & ( c); ret |= ((lut & (1<<7))==0) ? 0 : ( a) & ( b) & ( c); box_out.addDataFromShip(ret); } } == FleetSim ============================================================== == FPGA ============================================================== reg out_draining; wire [7:0] lut; genvar i; generate for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}]; end endgenerate assign lut = inLut_d[7:0]; always @(posedge clk) begin if (rst) begin `reset out_draining <= 0; end else begin `cleanup if (out_draining && `out_empty) begin `drain_in1 `drain_in2 `drain_in3 `drain_inLut out_draining <= 0; end if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin `fill_out out_draining <= 1; end end end == Test ================================================================= #expect 0 #expect -128 #expect 64 #expect -64 #expect 32 #expect -96 #expect 96 #expect -32 #expect 16 #expect -112 #expect 80 #expect -48 #expect 48 #expect -80 #expect 112 #expect -16 #expect 8 #expect -120 #expect 72 #expect -56 #expect 40 #expect -88 #expect 104 #expect -24 #expect 24 #expect -104 #expect 88 #expect -40 #expect 56 #expect -72 #expect 120 #expect -8 #expect 4 #expect -124 #expect 68 #expect -60 #expect 36 #expect -92 #expect 100 #expect -28 #expect 20 #expect -108 #expect 84 #expect -44 #expect 52 #expect -76 #expect 116 #expect -12 #expect 12 #expect -116 #expect 76 #expect -52 #expect 44 #expect -84 #expect 108 #expect -20 #expect 28 #expect -100 #expect 92 #expect -36 #expect 60 #expect -68 #expect 124 #expect -4 #expect 2 #expect -126 #expect 66 #expect -62 #expect 34 #expect -94 #expect 98 #expect -30 #expect 18 #expect -110 #expect 82 #expect -46 #expect 50 #expect -78 #expect 114 #expect -14 #expect 10 #expect -118 #expect 74 #expect -54 #expect 42 #expect -86 #expect 106 #expect -22 #expect 26 #expect -102 #expect 90 #expect -38 #expect 58 #expect -70 #expect 122 #expect -6 #expect 6 #expect -122 #expect 70 #expect -58 #expect 38 #expect -90 #expect 102 #expect -26 #expect 22 #expect -106 #expect 86 #expect -42 #expect 54 #expect -74 #expect 118 #expect -10 #expect 14 #expect -114 #expect 78 #expect -50 #expect 46 #expect -82 #expect 110 #expect -18 #expect 30 #expect -98 #expect 94 #expect -34 #expect 62 #expect -66 #expect 126 #expect -2 #expect 1 #expect -127 #expect 65 #expect -63 #expect 33 #expect -95 #expect 97 #expect -31 #expect 17 #expect -111 #expect 81 #expect -47 #expect 49 #expect -79 #expect 113 #expect -15 #expect 9 #expect -119 #expect 73 #expect -55 #expect 41 #expect -87 #expect 105 #expect -23 #expect 25 #expect -103 #expect 89 #expect -39 #expect 57 #expect -71 #expect 121 #expect -7 #expect 5 #expect -123 #expect 69 #expect -59 #expect 37 #expect -91 #expect 101 #expect -27 #expect 21 #expect -107 #expect 85 #expect -43 #expect 53 #expect -75 #expect 117 #expect -11 #expect 13 #expect -115 #expect 77 #expect -51 #expect 45 #expect -83 #expect 109 #expect -19 #expect 29 #expect -99 #expect 93 #expect -35 #expect 61 #expect -67 #expect 125 #expect -3 #expect 3 #expect -125 #expect 67 #expect -61 #expect 35 #expect -93 #expect 99 #expect -29 #expect 19 #expect -109 #expect 83 #expect -45 #expect 51 #expect -77 #expect 115 #expect -13 #expect 11 #expect -117 #expect 75 #expect -53 #expect 43 #expect -85 #expect 107 #expect -21 #expect 27 #expect -101 #expect 91 #expect -37 #expect 59 #expect -69 #expect 123 #expect -5 #expect 7 #expect -121 #expect 71 #expect -57 #expect 39 #expect -89 #expect 103 #expect -25 #expect 23 #expect -105 #expect 87 #expect -41 #expect 55 #expect -73 #expect 119 #expect -9 #expect 15 #expect -113 #expect 79 #expect -49 #expect 47 #expect -81 #expect 111 #expect -17 #expect 31 #expect -97 #expect 95 #expect -33 #expect 63 #expect -65 #expect 127 #expect -1 #ship debug : Debug #ship lut : Lut3 #ship alu : Alu lut.in1: set word= 85; set ilc=*; deliver; lut.in2: set word= 51; set ilc=*; deliver; lut.in3: set word= 15; set ilc=*; deliver; lut.out: set ilc=*; collect, send to debug.in; // cycle through truth tables using alu as INC alu.in2: set word= 1; set ilc=*; deliver; alu.inOp: set word= Alu.inOp[ADD]; set ilc=*; deliver; alu.in1: set word= 0; deliver; set ilc=*; recv, deliver; alu.out: set olc=2; head; recv token, collect, send to lut.inLut; send to alu.in1; tail; lut.inLut: set word= 0; deliver; set ilc=*; recv, deliver; // acks from debug ship trigger new truth tables debug.in: set ilc=63; recv, deliver, send token to alu.out; set ilc=63; recv, deliver, send token to alu.out; set ilc=63; recv, deliver, send token to alu.out; set ilc=63; recv, deliver, send token to alu.out; set ilc=4; recv, deliver, send token to alu.out; == Contributors ========================================================= Adam Megacz