ship: Random

== Ports ===========================================================
data  out:  out

== Constants ========================================================

== TeX ==============================================================
== Fleeterpreter ====================================================
    public void service() {
    }

== FleetSim ==============================================================

== FPGA ==============================================================

  reg [`WORDWIDTH-1:0] out_d;
  assign out_d_ = out_d;

  always @(posedge clk) begin
    if (rst) begin
      `reset
      out_d <= 0;
    end else begin
      `cleanup
      if (`out_empty) begin
        out_d <=  {out_d, out_d[17] ~^ out_d[10]}; 
        `fill_out
      end
    end
  end

== Test =================================================================
#skip

== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>