ship: Timer

== Ports ===========================================================
data  out:   out

== FPGA ==============================================================

  reg [37:0] out_d;
  assign out_d_ = out_d;

  always @(posedge clk) begin

    if (rst) begin
      `reset
      out_d <= 0;
    end else begin
      `cleanup

      out_d <= out_d+1;

      if (`out_empty) begin
         `fill_out
      end

    end
  end

== TeX ==============================================================

== Fleeterpreter ====================================================

public void service() {
    if (!box_out.readyForDataFromShip()) return;
    box_out.addDataFromShip(System.currentTimeMillis());
}

== FleetSim ==============================================================

== Constants =========================================================

== Test ==============================================================
#skip

== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>