40nm omega counter: switch design to use a timing constraint.
authorAdam Megacz <adam@megacz.com>
Sun, 20 Sep 2009 23:32:28 +0000 (16:32 -0700)
committerAdam Megacz <adam@megacz.com>
Sun, 20 Sep 2009 23:32:28 +0000 (16:32 -0700)
commit0a0cdeeaf1264a59c3f1dc4a2131780b46ba0481
tree0f159a8c0e6bdebd180ab414654a82cbd8f89f81
parentcbafca81451a452015ea365b3546c3bc0ac7bdbd
40nm omega counter: switch design to use a timing constraint.

Massive simplification; the design now runs at 20.0Ghz and has a
25ps/bit settling time in schematics with 4000 lambda of load on each
state wire and reasonable (100-400 lambda) loads on internal wires.
chips/omegaCounter/40nm/Makefile
chips/omegaCounter/40nm/electric/omegaCounter.jelib
chips/omegaCounter/40nm/electric/purpleFive.jelib
chips/omegaCounter/40nm/header.hsp
chips/omegaCounter/40nm/waveform.txt [new file with mode: 0644]