From 74c0578c820fde83bddd777a5474c7efc9684e09 Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Thu, 20 Aug 2009 15:12:26 -0700 Subject: [PATCH] add initial support for testing via blue-box jtag controller --- src/com/sun/vlsi/chips/marina/test/CmdArgs.java | 6 +++ src/com/sun/vlsi/chips/marina/test/Marina.java | 4 +- src/com/sun/vlsi/chips/marina/test/MarinaTest.java | 45 +++++++++++++++----- 3 files changed, 44 insertions(+), 11 deletions(-) diff --git a/src/com/sun/vlsi/chips/marina/test/CmdArgs.java b/src/com/sun/vlsi/chips/marina/test/CmdArgs.java index 2b1d237..05ecd4a 100644 --- a/src/com/sun/vlsi/chips/marina/test/CmdArgs.java +++ b/src/com/sun/vlsi/chips/marina/test/CmdArgs.java @@ -20,6 +20,7 @@ public class CmdArgs { public boolean testChains = false; public boolean useVerilog = false; public boolean useHsim = false; + public boolean silicon = false; public Station station=Station.ONE; public float vdd, temp; public boolean init; @@ -31,6 +32,7 @@ public class CmdArgs { System.out.println("Options: -testNum select which test to run"); System.out.println(" -verilog use Verilog-XL simulator rather than NanoSim"); System.out.println(" -hsim use Hsim simulator rather than NanoSim"); + System.out.println(" -silicon use actual silicon chip via blue box"); System.out.println(" -testChains invoke testAllChains() on startup"); System.out.println(" -vdd "); System.out.println(" -temp "); @@ -78,8 +80,10 @@ public class CmdArgs { mode = CmdArgs.Mode.WHOLE_CHIP_SCHEMATIC_PARASITICS; } else if (args[i].equals("-chipLay")) { mode = CmdArgs.Mode.WHOLE_CHIP_LAYOUT_PARASITICS; + /* } else if (args[i].equals("-silicon")) { mode = CmdArgs.Mode.TEST_SILICON; + */ } else if (args[i].equals("-jtagShift")) { jtagShift = true; } else if (args[i].equals("-testChains")) { @@ -88,6 +92,8 @@ public class CmdArgs { useVerilog = true; } else if (args[i].equals("-hsim")) { useHsim = true; + } else if (args[i].equals("-silicon")) { + silicon = true; } else { System.out.println("Bad argument: "+args[i]); usage(); diff --git a/src/com/sun/vlsi/chips/marina/test/Marina.java b/src/com/sun/vlsi/chips/marina/test/Marina.java index f878f47..dfc2b59 100644 --- a/src/com/sun/vlsi/chips/marina/test/Marina.java +++ b/src/com/sun/vlsi/chips/marina/test/Marina.java @@ -250,7 +250,7 @@ public class Marina { data.idle(); instrIn.idle(); - } else { + } else if (model instanceof NanosimModel) { NanosimModel nModel = (NanosimModel) model; /* nModel.setNodeVoltage(prefix+"sid[9]",1.0); @@ -266,6 +266,8 @@ public class Marina { nModel.waitNS(WIDTH); nModel.setNodeVoltage(MASTER_CLEAR,0.0); nModel.waitNS(1); + } else { + prln("FIXME!"); } resetAfterMasterClear(); } diff --git a/src/com/sun/vlsi/chips/marina/test/MarinaTest.java b/src/com/sun/vlsi/chips/marina/test/MarinaTest.java index 91a3944..42e3486 100644 --- a/src/com/sun/vlsi/chips/marina/test/MarinaTest.java +++ b/src/com/sun/vlsi/chips/marina/test/MarinaTest.java @@ -34,6 +34,7 @@ import edu.berkeley.fleet.api.Instruction.Set.SetDest; import edu.berkeley.fleet.api.Instruction.Set.SetSource; import edu.berkeley.fleet.marina.MarinaFleet; import edu.berkeley.fleet.marina.MarinaPath; +import com.sun.async.test.*; /** * Tests for Marina @@ -214,20 +215,38 @@ public class MarinaTest { fatal(true, "unrecognized CmdArgs.Mode"); return; } + model = cmdArgs.useVerilog ? new VerilogModel() : cmdArgs.useHsim ? new HsimModel() + : cmdArgs.silicon + ? new SiliconChip() : new NanosimModel(); - ((SimulationModel)model).setOptimizedDirectReadsWrites(true); + if (model instanceof SimulationModel) + ((SimulationModel)model).setOptimizedDirectReadsWrites(true); CYCLE_TIME_NS = cmdArgs.useVerilog ? (100*20) : 0.250; - int khz = model instanceof VerilogModel ? 100000 : cmdArgs.jtagShift ? 20000 : 1000000; - - prln("constructing jtag controller"); - JtagTester tester = ((SimulationModel)model).createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDO"); - tester.printInfo = false; + int khz = + model instanceof VerilogModel + ? 100000 + : cmdArgs.jtagShift + ? 20000 + : model instanceof ChipModel + ? 1 + : 1000000; + + System.err.println("constructing jtag controller"); + JtagTester tester = + model instanceof SimulationModel + ? ((SimulationModel)model).createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDO") + : new Netscan4("jtag3", 2); + Logger.setLogInits(true); + tester.setLogSets(true); + tester.setLogOthers(true); + tester.setAllLogging(true); + tester.printInfo = true; ChainControls ccs = new ChainControls(); PowerChannel pc = new ManualPowerChannel("pc", false); @@ -274,13 +293,18 @@ public class MarinaTest { ((SimulationModel)model).start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift); else if (model instanceof HsimModel) ((SimulationModel)model).start("hsim64", netListName, 0, !cmdArgs.jtagShift); - else + else if (model instanceof NanosimModel) ((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift); + else + {} prln("model started"); model.waitNS(1000); prln("deasserting master clear"); - ((SimulationModel)model).setNodeState(Marina.MASTER_CLEAR, 0); + if (model instanceof SimulationModel) + ((SimulationModel)model).setNodeState(Marina.MASTER_CLEAR, 0); + else + prln("FIXME: need to deassert master clear"); model.waitNS(1000); if (cmdArgs.testNum!=0 && cmdArgs.testNum!=1) { @@ -289,8 +313,9 @@ public class MarinaTest { } doOneTest(cmdArgs.testNum); - - ((SimulationModel)model).finish(); + + if (model instanceof SimulationModel) + ((SimulationModel)model).finish(); } private void doSilicon() { model = new SiliconChip(); -- 1.7.10.4