From ba5f7c0fabc78385cbc70f0f84fa6c32ac9154ef Mon Sep 17 00:00:00 2001
From: Adam Megacz <adam.megacz@sun.com>
Date: Tue, 21 Jul 2009 01:12:17 +0000
Subject: [PATCH] equalized pull-downs in state wire drivers, works

---
 electric/omegaCounter.jelib |   22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/electric/omegaCounter.jelib b/electric/omegaCounter.jelib
index 66ce661..749207c 100644
--- a/electric/omegaCounter.jelib
+++ b/electric/omegaCounter.jelib
@@ -564,7 +564,7 @@ Edisable|disableLO|D5G2;X-2;Y-2;|pin@38||I
 X
 
 # Cell oneBit;1{sch}
-ConeBit;1{sch}||schematic|1242942044308|1248137636733|
+ConeBit;1{sch}||schematic|1242942044308|1248138242887|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||1.5|17.5||||
 NOff-Page|conn@1||-87|19.5|||RR|
@@ -909,15 +909,15 @@ Estate[1]|state|D5G2;X2.5;|pin@6||B
 X
 
 # Cell predCond;1{sch}
-CpredCond;1{sch}||schematic|1227920907034|1247964921320||ATTR_X(D5G4;HNPX-23;Y28;)S@X
-IredFive:PMOS;1{ic}|PMOS@0||-7.5|7.5|||D5G4;|ATTR_Delay(D5G1;NPX-2.5;Y-1.5;)I100|ATTR_X(D5G1.5;NPX-2.5;Y1.5;)S2
-IredFive:PMOS;1{ic}|PMOS@1||-5.5|7.5|X||D5G4;|ATTR_Delay(D5G1;NPX-4.5;Y1.5;)I100|ATTR_X(D5G1.5;NPX-3.5;Y-1.5;)S2
+CpredCond;1{sch}||schematic|1227920907034|1248138341053||ATTR_X(D5G4;HNPX-23;Y28;)S@X
+IredFive:PMOS;1{ic}|PMOS@0||-7.5|7.5|||D5G4;|ATTR_X(D5G1.5;NOLPX-3;Y1.5;)S@X
+IredFive:PMOS;1{ic}|PMOS@1||-5.5|7.5|X||D5G4;|ATTR_X(D5G1.5;NOLPX-3;Y1.5;)S@X
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-23|0.5||||
 NOff-Page|conn@2||42.75|0.5|||X|
 NOff-Page|conn@4||9.5|-10|||X|
 NOff-Page|conn@5||12|12|||RR|
-IredFive:nms2b;1{ic}|nms2b@0||-6.5|-10|X||D5G4;|ATTR_Delay(D5G1;NPX3;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX-2.25;)S@X
+IredFive:nms2b;1{ic}|nms2b@0||-6.5|-10|X||D5G4;|ATTR_X(D5FLeave alone;G1.5;NOLPX-2.25;)S@X
 Ngeneric:Invisible-Pin|pin@0||-0.5|39|||||ART_message(D5G5;)SpredCondMSC
 Ngeneric:Invisible-Pin|pin@1||0|35|||||ART_message(D5G3;)Sam 13 Jul 2009
 NWire_Pin|pin@29||-18|-6|||X|
@@ -933,7 +933,7 @@ NWire_Pin|pin@64||-1|7.5||||
 NWire_Pin|pin@74||-6.5|10||||
 NWire_Pin|pin@76||-6.5|-4||||
 NWire_Pin|pin@77||-11|-6||||
-IredFive:pms1;2{ic}|pms1@1||-6.5|12|X||D5G4;|ATTR_Delay(D5G1;NPX-2;Y-1.5;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX4.25;Y3;)S2
+IredFive:pms1;2{ic}|pms1@1||-6.5|12|X||D5G4;|ATTR_X(D5FLeave alone;G1.5;NOLPX-2.25;Y2.5;)S@X
 IpredCond;1{ic}|pred10wM@1||28.5|25|||D5G4;
 IpredCond;2{ic}|predCond@0||11.5|25|||D5G4;|ATTR_X(D5G1;NPX-0.25;Y-5.25;)S@X
 Awire|net@90|||0|pin@41||34|0.5|pin@36||-6.5|0.5
@@ -1179,10 +1179,10 @@ Esucc|state|D5G2;X4.5;|pin@2||B
 X
 
 # Cell succCond;1{sch}
-CsuccCond;1{sch}||schematic|1188777360591|1247965107296||ATTR_X(D5G1;HNPX-21;Y26;)I8
-IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@0||-3|-4|||D0G4;|ATTR_Delay(D5G1;NPX-2;Y-2.5;)I100|ATTR_X(D5G1.5;NPX-0.5;Y3;)S1
-IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@1||3|-4|X||D0G4;|ATTR_Delay(D5G1;NPX-2;Y-2;)I100|ATTR_X(D5G1.5;NPX-0.5;Y2.5;)S1
-IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@2||0|-12|X||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NPX3.5;Y0.5;)S1
+CsuccCond;1{sch}||schematic|1188777360591|1248138297399||ATTR_X(D5G1;HNPX-21;Y26;)I8
+IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@0||-3|-4|||D0G4;|ATTR_X(D5G1.5;NOLPX-0.5;Y3;)S@X
+IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@1||3|-4|X||D0G4;|ATTR_X(D5G1.5;NOLPX-1.5;Y2;)S@X
+IorangeTSMC090nm:NMOSx;1{ic}|NMOSx@2||0|-12|X||D0G4;|ATTR_X(D5G1.5;NOLPX-2.5;Y-2;)S@X
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-17|0||||
 NOff-Page|conn@1||23.5|0||||
@@ -1203,7 +1203,7 @@ NWire_Pin|pin@60||0|-8||||
 NWire_Pin|pin@61||0|0||||
 NWire_Pin|pin@62||9|10||||
 NWire_Pin|pin@63||-9|6||||
-IredFive:pms2;1{ic}|pms2@0||0|10|X||D0G4;|ATTR_Delay(D5G1;NPX-3;Y-1.5;)I100|ATTR_X(D5G1.5;NOLPX1.25;Y6;)S@X
+IredFive:pms2;1{ic}|pms2@0||0|10|X||D0G4;|ATTR_X(D5G1.5;NOLPX1.25;Y6;)S@X
 IsuccCond;1{ic}|sucDri20@2||36|16|||D5G4;
 IsuccCond;2{ic}|succCond@1||21|17|||D5G4;|ATTR_X(D5G1;NPX-0.5;Y5;)I8
 Awire|net@109|||2700|pin@39||-9|-4|pin@37||-9|0
-- 
1.7.10.4