From d991892010b621b544f7cd50e7bac1862eeff5f6 Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Sat, 29 Aug 2009 18:10:29 -0700 Subject: [PATCH] clean gunk out of am42 --- chips/f2/doc/am42/Makefile | 25 ++ chips/f2/doc/am42/am42.tex | 651 +++++--------------------------------------- 2 files changed, 100 insertions(+), 576 deletions(-) create mode 100644 chips/f2/doc/am42/Makefile diff --git a/chips/f2/doc/am42/Makefile b/chips/f2/doc/am42/Makefile new file mode 100644 index 0000000..6e4e97e --- /dev/null +++ b/chips/f2/doc/am42/Makefile @@ -0,0 +1,25 @@ + +inkscape = DISPLAY= /Applications/Inkscape.app/Contents//Resources/bin/inkscape -z + +default: am42.pdf + open am42.pdf + +am42.pdf: am42.tex + pdflatex am42.tex + +am42.pdf: am42.tex + pdflatex am42.tex + +%.eps: %.svg + $(inkscape) -D $^ --export-eps=$@ + +%.pdf: %.eps + epstopdf $^ --outfile=$@ + +publish: am42.pdf + aklog research.cs.berkeley.edu + cp am42.pdf /afs/research.cs.berkeley.edu/class/fleet/website/docs/people/adam.megacz/am42/`date +%d-%b-%Y | tr A-Z a-z`.pdf + cd /afs/research.cs.berkeley.edu/class/fleet/website/docs/people/adam.megacz/am42/; ln -sf `date +%d-%b-%Y | tr A-Z a-z`.pdf am42-latest.pdf + echo + emacs -nw ~/wix/src/research.cs.berkeley.edu/fleet/docs/index.wix + cd ~/proj/wix; make \ No newline at end of file diff --git a/chips/f2/doc/am42/am42.tex b/chips/f2/doc/am42/am42.tex index 09ab627..c6194ef 100644 --- a/chips/f2/doc/am42/am42.tex +++ b/chips/f2/doc/am42/am42.tex @@ -4,55 +4,15 @@ \usepackage{epsfig} \usepackage{color} \usepackage{bytefield1} -\usepackage{wrapfig} -\usepackage{stmaryrd} -\usepackage{subfigure} -\usepackage{syntax} \usepackage{comment} \usepackage{fancyhdr} -\usepackage{lastpage} -\usepackage{multirow} -\usepackage{multicol} -\usepackage{rotating} \include{megacz} \bibliographystyle{alpha} \pagestyle{fancyplain} \definecolor{light}{gray}{0.7} -\setlength{\marginparwidth}{1.2in} -\let\oldmarginpar\marginpar -\renewcommand\marginpar[1]{\-\oldmarginpar[\raggedleft\footnotesize #1]% -{\raggedright\footnotesize #1}} - - -\newcommand{\footnoteremember}[2]{ - \footnote{#2} - \newcounter{#1} - \setcounter{#1}{\value{footnote}} -} \newcommand{\footnoterecall}[1]{ - \footnotemark[\value{#1}] -} - -%\pdfpagewidth 8.5in -%\pdfpageheight 11in -%\topmargin 0in -\textheight 8.2in -%\textwidth 6.0in -%\oddsidemargin 0.25in -%\evensidemargin 0.25in -%\headwidth 6.0in -\def\to{\ $\rightarrow$\ } - -\def\docnum{AM33} - -\author{ -\normalsize{ -\begin{tabular}{c} -\end{tabular}} -} - -\title{\vspace{-1cm}AM33: The FleetTwo Dock +\title{\vspace{-1cm}AM42: The F2 Dock \\ {\normalsize Adam Megacz @@ -63,9 +23,12 @@ Adam Megacz \maketitle \begin{abstract} -Changes: + +To Do: +\\ \begin{verbatim} + - tokenhood as address bit - signal/path boundary/etc - Rename EPI and OD to something more meaningful @@ -76,7 +39,8 @@ Changes: - single "predicate" flag - Suggestion that there should be a "T" flag - Get rid of "shadow latch" for literals? - - unify flags and signal bit by saying that the dock can see the upper X bits of a word? + - unify flags and signal bit by saying that the dock can + see the upper X bits of a word? - should have a way to set just the upper X bits of the word - flags are actually part of the data latch! - the signal bit(s) belong to the Destination (or is it the Path?) @@ -84,143 +48,21 @@ Changes: - How do you get a runtime count value to an input dock? - Simplify the whole c-flag/signal-bit situation - tokenhood should be LITERALLY an address bit! + \end{verbatim} \begin{tabular}{rl} -\color{red} -09-Aug -& \color{red} Removed the explicit ``decrement loop counter'' instruction \\ -& \color{red} Renamed {\tt D}-flag to {\tt Z}-flag \\ -\color{red} -21-Jun -& \color{red} Moved the {\tt P} (predicate) field to the MSB end of the word \\ -& \color{red} Changed to a single counter, full word width \\ -& \color{red} Included one extra Marina erratum I had forgotten \\ -& \color{red} Changed encoding of {\tt flush} to match internal encoding\\ -\color{black} -25-May -& Added errata for Kessel counter on Marina test chip \\ -18-May -& Added errata for Marina test chip \\ -17-Feb -& Clarified setting of the {\tt C}-flag\color{black}\\ -& Removed {\tt OS} bit\color{black}\\ -& Changed instruction length from 26 bits to 25\color{black}\\ -& Updated which bits are used when the {\tt Path} latch captures from the data predecessor\color{black}\\ -05-Jan -& Fixed a one-word typo \\ -02-Jan -& Added {\tt head} instruction \\ -& Lengthened external encoding of {\tt tail} instruction by one bit \\ -& Added {\tt abort} instruction \\ -& Removed {\tt OS} field from instructions \\ -& Renamed the {\tt Z}-flag (olc {\bf Z}ero) to the {\tt D}-flag (loop {\bf D}one)\\ -19-Dec -& Updated diagram in section 3 to put dispatch path near MSB\\ -& Changed DP[37:25] to DP[37:27]\\ -& Added note on page 4 regarding previous\\ -14-Nov -& Roll back ``Distinguish {\tt Z}-flag from OLC=0'' \\ -& Clarify what ``{\tt X-Extended}'' means \\ -& Change C-bit source selector from {\tt Di} to {\tt Dc} \\ -07-Nov -& Distinguish {\tt Z}-flag from OLC=0\\ -& Add {\tt flush} instruction\\ -& Change {\t I} bit from ``Interruptable'' to ``Immune''\\ -20-Sep -& Update hatch description to match \href{http://fleet.cs.berkeley.edu/docs/people/ivan.e.sutherland/ies50-Requeue.State.Diagram.pdf}{IES50} \\ -28-Aug -& Note that decision to requeue is based on value of OLC {\it before} execution\\ -& Note that decision to open the hatch is based on value of {\tt OS} bit\\ -%10-Jul -%& Added {\tt OLC=0} predicate \\ -%& Eliminated {\tt TAPL} (made possible by previous change) \\ -%& Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\ -%09-Jul -%& Fixed a few typos \\ -%& Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\ -%& Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\ -%16-Jun -%& When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\ -%& Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\ -%11-Jun -%& Changed all uses of ``Payload'' to ``Immediate'' \color{black} (not in red) \\ -%& Reworked encoding of {\tt set} instruction \\ -%\color{black} -%06-Jun -%& Factored in Russell Kao's comments (thanks!)\\ -%& Added mechanism for setting C-flag from fabric even on outboxes\\ -%05-Jun -%& Made {\tt OLC} test a predicate-controlled condition\\ -%& Rewrote ``on deck'' section \\ -%& Added ``{\tt unset}'' value for {\tt ILC}\\ -%& Changed {\tt DP} to {\tt DataPredecessor} for clarity\\ -%\color{black} -%30-Apr -%& added comment about address-to-path ship \\ -%& changed {\tt DST} field of {\tt set} instruction from 2 bits to 3 \\ -%& changed the order of instructions in the encoding map \\ -%23-Apr -%& added epilogue fifo to diagrams \\ -%& indicated that a token sent to the instruction port is treated as a torpedo \\ -%18-Apr -%& replaced {\tt setInner}, {\tt setOuter}, {\tt setFlags} with unified {\tt set} instruction \\ -%& replaced {\tt literal} with {\tt shift} instruction \\ -%17-Apr -%& Made all instructions except {\tt setOuter} depend on {\tt OLC>0} \\ -%& Removed ability to manually set the {\tt C} flag \\ -%& Expanded predicate field to three bits \\ -%& New literals scheme (via shifting) \\ -%& Instruction encoding changes made at Ivan's request (for layout purposes) \\ -%& Added summary of instruction encodings on last page \\ -%07-Apr -%& removed ``+'' from ``potentially torpedoable'' row where it does not occur in Execute \\ -%06-Apr -%& extended {\tt LiteralPath} to 13 bits (impl need not use all of them) \\ -%& update table 3.1.2 \\ -%& rename {\tt S} flag to {\tt C} \\ -%& noted that {\tt setFlags} can be used as {\tt nop} \\ -%29-Mar -%& removed the {\tt L} flag (epilogues can now do this) \\ -%& removed {\tt take\{Inner|Outer\}LoopCounter} instructions \\ -%& renamed {\tt data} instruction to {\tt literal} \\ -%& renamed {\tt send} instruction to {\tt move} \\ -%23-Mar -%& added ``if its predicate is true'' to repeat count \\ -%& added note that red wires do not contact ships \\ -%& changed name of {\tt flags} instruction to {\tt setFlags} \\ -%& removed black dot from diagrams \\ -%& changed {\tt OL} (Outer Loop participant) to {\tt OS} (One Shot) and inverted polarity \\ -%& indicated that the death of the {\tt tail} instruction is what causes the hatch to be unsealed \\ -%& indicated that only {\tt send} instructions which wait for data are torpedoable \\ -%& added section ``Torpedo Details'' \\ -%& removed {\tt torpedo} instruction \\ -%12-Mar -%\color{black} -%& renamed loop+repeat to outer+inner (not in red) \\ -%& renamed {\tt Z} flag to {\tt L} flag (not in red) \\ -%& rewrote ``inner and outer loops'' section \\ -%& updated all diagrams \\ -%\color{black} -%7-Mar -%& Moved address bits to the LSB-side of a 37-bit instruction \\ -%& Added {\it micro-instruction} and {\it composite instruction} terms \\ -%& Removed the {\tt DL} field, added {\tt decrement} mode to {\tt loop} \\ -%& Created the {\tt Hold} field \\ -%& Changed how ReLooping works \\ -%& Removed {\tt clog}, {\tt unclog}, {\tt interrupt}, and {\tt massacre} \\ + +29-Aug +& Initial Version \\ \end{tabular} \end{abstract} \vfill -\begin{center} -\epsfig{file=all,height=1.5in} -\epsfig{file=overview-new,height=1.5in} -\end{center} - \pagebreak +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \section{Overview of Fleet} A Fleet processor is organized around a {\it switch fabric}, which is @@ -233,9 +75,9 @@ A {\it path} specifies a route through the switch fabric from a particular {\it source} to a particular {\it destination}. The combination of a path and a single word to be delivered is called a {\it packet}. The switch fabric carries packets from their sources to -their destinations. Each dock has \color{red}four\color{black}\ -destinations: one each for {\it instructions}, \color{red}{\it - torpedoes}, {\it tokens},\color{black}\ and {\it words}. A Fleet is +their destinations. Each dock has four\ +destinations: one each for {\it instructions}, {\it + torpedoes}, {\it tokens},\ and {\it words}. A Fleet is programmed by depositing instruction packets into the switch fabric with paths that will lead them to instruction destinations of the docks at which they are to execute. @@ -251,27 +93,15 @@ Packets sent to token and torpedo destinations carry no payload. Such packets consume less energy than instruction packets or word packets. -\begin{center} -\epsfig{file=overview-new,width=2.5in}\\ -{\it Overview of a Fleet processor; dark gray shading represents the - switch fabric, ships are shown in light gray, and docks are shown in blue.} -\end{center} -\color{black} - +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \pagebreak - \section{The FleetTwo Dock} The diagram below represents a conceptual view of the interface between ships and the switch fabric; actual implementation circuitry may differ. -\begin{center} -\epsfig{file=all,width=3.5in}\\ -{\it An ``input'' dock and ``output'' dock connected to a ship. Solid - blue lines carry either tokens or data words, red lines carry either - instructions or torpedoes, and dashed lines carry only tokens.} -\end{center} +X Each dock consists of a {\it data latch}, which is as wide as a single machine word and a circular {\it instruction fifo} of @@ -295,11 +125,11 @@ the signal bit is used to pass control values between docks. Note that paths terminating at an {\it instruction} destination need not have a signal bit. -\color{red} + Source-sequence guarantee. Shared across instruction/torpedo (?) and token/word destinations. -\color{black} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \pagebreak \section{Instructions} @@ -311,8 +141,8 @@ instruction has arrived at this output dock, it is {\it dispatched} by sending it to the {\it instruction destination} of the dock at which it is to execute. -Each instruction is 25\color{black}\ bits long, which makes -it possible for an instruction and an 12\color{black}-bit +Each instruction is 25\ bits long, which makes +it possible for an instruction and an 12-bit path to fit in a single word of memory. This path is the path from the {\it dispatching} dock to the {\it executing} dock. @@ -325,9 +155,9 @@ the {\it dispatching} dock to the {\it executing} dock. \bitbox{12}{dispatch path} \bitbox{25}{instruction} \end{bytefield}} -\color{black} -Note that the 12\color{black}\ bit {\tt dispatch path} + +Note that the 12\ bit {\tt dispatch path} field is not the same width as the 13 bit {\tt Immediate} path field in the {\tt move} instruction, which in turn may not be the same width as the actual path latches in the switch fabric. @@ -342,33 +172,6 @@ specify a path which terminates at an instruction destination (never a data destination), and because instruction destinations ignore the signal bit, certain optimizations may be possible. -%\subsection{Life Cycle of an Instruction} -% -%The diagram below shows an input dock for purposes of illustration: -% -%\begin{center} -%\epsfig{file=in,width=4in}\\ -%{\it an input dock} -%\end{center} -% -%\color{black} -% -%\begin{center} -%\epsfig{file=out,width=4in}\\ -%{\it an output dock} -%\end{center} - -%\subsection{Format of an Instruction} -% -%All instruction words have the following format: -% -% -% -%The {\tt P} bits are a {\it predicate}; this holds a code which -%indicates if the instruction should be executed or ignored depending -%on the state of flags in the dock. Note that {\tt head} and {\tt -%tail} instructions do not have {\tt P} fields. - \subsection{Loop Counter} @@ -377,42 +180,28 @@ consisting of only one {\tt move} instruction and {\it outer} loops of multiple instructions of any type. Inner loops may be nested within an outer loop, but no other nesting of loops is allowed. -The dock has \color{red}one loop counter, called {\tt LC}. It is the +The dock has one loop counter, called {\tt LC}. It is the same width as a word carried through the switch fabric (37 bits). -\color{black} - \subsection{Flags} -The dock has four flags: {\tt A}, {\tt B}, -{\tt C}, and \color{red}{\tt Z}\color{black}. +The dock has four flags: {\tt A}, {\tt B}, {\tt C}, and {\tt Z}. \begin{itemize} \item The {\tt A} and {\tt B} flags are general-purpose flags which may be set and cleared by the programmer. -%\item -% -% The {\tt L} flag, known as the {\it last} flag, is set whenever -% the value in the outer counter ({\tt OLC}) is one, -\color{black} -% indicating -% that the dock is in the midst of the last iteration of an -% outer loop. This flag can be used to perform certain -% operations (such as sending a completion token) only on the last -% iteration of an outer loop. - \item The {\tt C} flag is known as the {\it control} flag, and may be set by the {\tt move} instruction based on information from the ship or from an inbound packet. See the {\tt move} instruction for further details. -\item The \color{red}{\tt Z}\color{black}\ flag is known as the - \color{red}{\it zero}\color{black}\ flag. The \color{red}{\tt - Z}\color{black}\ flag is {\it set} whenever the {\tt LC} is zero. - In an actual implementation the \color{red}{\tt Z}\color{black}\ +\item The {\tt Z}\ flag is known as the + {\it zero}\ flag. The {\tt + Z}\ flag is {\it set} whenever the {\tt LC} is zero. + In an actual implementation the {\tt Z}\ flag might require an actual latch; it might simply be derived - from the ``zeroness'' of the {\tt LC}.\color{black} + from the ``zeroness'' of the {\tt LC}. \end{itemize} @@ -428,7 +217,7 @@ field marked {\tt P}, which specifies a {\it predicate}. \bitheader[b]{0,21,22,24}\\ \bitbox{3}{P} \bitbox[tbr]{22}{} -\color{black} + \end{bytefield}}}} \end{center} @@ -453,13 +242,6 @@ Code & Execute if \\\hline \pagebreak -\begin{wrapfigure}{r}{40mm} - \begin{center} -\epsfig{file=requeue,height=1.5in}\\ - \end{center} - \caption{{\it the requeue stage}} -\end{wrapfigure} - \subsection{The Requeue Stage} The requeue stage has two inputs, which will be referred to as the @@ -513,20 +295,12 @@ transitions back to the {\sc Updating} state. Note that {\tt abort} instructions include a predicate; an {\tt abort} instruction whose predicate is not met will not cause this transition. -\color{black} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \pagebreak \section{Instructions} -%The dock supports four instructions: -%{\tt move} (variants: {\tt moveto}, {\tt dispatch}), -%{\tt shift}, -%{\tt set}, and -%{\tt tail}. -%\color{black} - - \subsection{{\tt move}} \newcommand{\bitsMove}{\setlength{\bitwidth}{5mm} @@ -535,12 +309,12 @@ predicate is not met will not cause this transition. \bitheader[b]{14-21}\\ \color{light} \bitbox{3}{P} -\color{black} -\color{red} + + \bitbox{1}{0} \bitbox{1}{R} \bitbox{1}{I} -\color{black} + \bitbox{1}{\tt Ti} \bitbox{1}{\tt Di} \bitbox{1}{\tt Dc} @@ -551,7 +325,7 @@ predicate is not met will not cause this transition. \begin{bytefield}{25} \bitheader[b]{0,12,13}\\ - \bitbox[1]{10}{\raggedleft {\tt moveto} ({\tt Immediate\to Path})} + \bitbox[1]{10}{\raggedleft {\tt moveto} ({\tt Immediate$\to$ Path})} \bitbox[r]{1}{} \bitbox{1}{\tt 1} \bitbox{13}{\tt Immediate} @@ -559,13 +333,12 @@ predicate is not met will not cause this transition. \begin{bytefield}{25} \bitheader[b]{11,12,13}\\ - \bitbox[1]{10}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:26\color{black}]\to Path}})\ \ } + \bitbox[1]{10}{\raggedleft {\tt dispatch} ({\footnotesize {\tt DataPredecessor[37:26]$\to$ Path}})\ \ } \bitbox[r]{1}{} \bitbox{1}{\tt 0} \bitbox{1}{\tt 1} \color{light} \bitbox[trb]{12}{} -\color{black} \end{bytefield} \begin{bytefield}{25} @@ -574,13 +347,10 @@ predicate is not met will not cause this transition. \bitbox[r]{1}{} \bitbox{1}{\tt 0} \bitbox{1}{\tt 0} -\color{red} \bitbox{1}{\tt 0} \color{light} \bitbox[trb]{11}{} -\color{black} \end{bytefield} - } \bitsMove @@ -595,7 +365,7 @@ predicate is not met will not cause this transition. The data successor and token successor must both be empty in order for a {\tt move} instruction to attempt execution. -\color{red} + If the {\tt S} bit is set (not shown -- there is no space left!), the {\tt move} instruction will subtract one from the {\tt LC} counter each time it executes. @@ -607,16 +377,16 @@ If the {\tt R} bit is set, the {\tt move} instruction will execute repeatedly until its predicate no longer holds (or a torpedo strikes). An ``infinite'' or ``standing'' move can be achieved by setting the {\tt R} bit and clearing the {\tt S} bit. -\color{black} + \subsection*{Torpedoes} The {\tt I} bit stands for {\tt Immune}, and indicates if the instruction is immune to torpedoes. If a {\tt move} instruction which is not immune is waiting to execute and a torpedo is lying in wait, -the torpedo {\it strikes}. \color{red}When a torpedo strikes, the +the torpedo {\it strikes}. When a torpedo strikes, the {\tt move} instruction and the torpedo are both consumed and the {\tt - LC} is set to zero.\color{black} + LC} is set to zero. \subsection*{The C Flag} @@ -632,7 +402,7 @@ be set: Dc} bit is not set, the {\tt C} flag is set to the signal bit of the incoming packet. \end{itemize} -\color{black} + \subsection*{Flushing} @@ -651,11 +421,11 @@ being delivered. \bitbox{1}{\tt 1} \bitbox{1}{\tt 0} \bitbox{1}{\tt 0} -\color{red} + \bitbox{1}{\tt 0} \bitbox{1}{\tt 0} \bitbox{1}{\tt 1} -\color{black} + \bitbox{11}{} \end{bytefield}}} \bitsFlush @@ -669,59 +439,51 @@ all, of the indicators are set, the ship must drain {\it only the data take no action. If none of the flushing indicators was set, the ship fires normally. -\color{black} -\pagebreak +\pagebreak \subsection{{\tt set}} The {\tt set} command is used to set the data latch, the flags, or the loop counter. \newcommand{\bitsSet}{ -{\tt -\begin{bytefield}{25} +{\tt\begin{bytefield}{25} \bitheader[b]{19-21}\\ \color{light} \bitbox{3}{P} -\color{black} -\color{red} \bitbox{1}{1} \bitbox{1}{0} \bitbox{1}{1} -\color{black} \color{light} \bitbox{4}{Dest} \bitbox{3}{Src} \bitbox{12}{} -\color{black} \end{bytefield}} \begin{bytefield}{25} \bitheader[b]{0,11-18}\\ - \bitbox[1]{5}{\raggedleft {\tt Immediate}\to{\tt LC}} + \bitbox[1]{5}{\raggedleft {\tt Immediate}$\to${\tt LC}} \bitbox[r]{1}{} - \bitbox{4}{\tt 1000\color{black}} + \bitbox{4}{\tt 1000} \bitbox{3}{\tt 100} - \color{red} \bitbox{12}{\tt Immediate} - \color{black} \end{bytefield} \begin{bytefield}{25} \bitheader[b]{12-18}\\ - \bitbox[1]{5}{\raggedleft {\tt Data Latch}\to{\tt LC}} + \bitbox[1]{5}{\raggedleft {\tt Data Latch}$\to${\tt LC}} \bitbox[r]{1}{} - \bitbox{4}{\tt 1000\color{black}} + \bitbox{4}{\tt 1000} \bitbox{3}{\tt 010} \bitbox{12}{} \end{bytefield} \begin{bytefield}{25} \bitheader[b]{0,13-18}\\ - \bitbox[1]{5}{\raggedleft \footnotesize {\tt Sign-Extended Immediate}\to{\tt Data Latch}} + \bitbox[1]{5}{\raggedleft \footnotesize {\tt Sign-Extended Immediate}$\to${\tt Data Latch}} \bitbox[r]{1}{} - \bitbox{4}{\tt 0010\color{black}} + \bitbox{4}{\tt 0010} \bitbox{1}{\begin{minipage}{0.5cm}{ \begin{center} \tt{\footnotesize{Si @@ -736,12 +498,12 @@ loop counter. \bitheader[b]{0,5,6,11,15-18}\\ \bitbox[1]{5}{\raggedleft {\tt Update Flags}} \bitbox[r]{1}{} - \bitbox{4}{\tt 0001\color{black}} + \bitbox{4}{\tt 0001} \bitbox{3}{} \bitbox{6}{\tt nextA} \bitbox{6}{\tt nextB} \end{bytefield} -\color{black} + } \bitsSet @@ -756,7 +518,7 @@ The {\tt Sign-Extended Immediate} instruction copies the {\tt Immediate} field into the least significant bits of the data latch. All other bits of the data latch are filled with a copy of the bit marked ``{\tt Sign}.'' -\color{black} + Each of the {\tt nextA} and {\tt nextB} fields has the following structure, and indicates which old flag values should be logically @@ -783,7 +545,7 @@ is zero. Note also that it is possible to produce a {\tt 1} by {\tt be used to create a {\tt nop} (no-op) by setting each flag to itself. -\color{black} + \pagebreak \subsection{{\tt shift}} @@ -805,16 +567,16 @@ into the data latch \shiftImmediateSize\ bits at a time. \bitheader[b]{0,18-21}\\ \color{light} \bitbox{3}{P} -\color{black} -\color{red} + + \bitbox{1}{1} \bitbox{1}{0} \bitbox{1}{0} -\color{black} + \bitbox{\shiftImmediateSize}{Immediate} \end{bytefield}} } -\bitsShift +%\bitsShift The FleetTwo implementation is likely to have an unarchitected ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded @@ -822,7 +584,7 @@ with the literal {\it at the time that the {\tt shift} instruction comes on deck}. This latch is then copied into the data latch when the instruction executes. -\color{black} + \subsection{{\tt abort}} \newcommand{\bitsAbort}{\setlength{\bitwidth}{5mm} @@ -831,12 +593,12 @@ the instruction executes. \bitheader[b]{18-21}\\ \color{light} \bitbox{3}{P} -\color{black} -\color{red} + + \bitbox{1}{1} \bitbox{1}{1} \bitbox{1}{0} -\color{black} + \bitbox{1}{0} \color{light} \bitbox[tbr]{18}{} @@ -854,12 +616,12 @@ the Requeue Stage for further details. \bitheader[b]{18-21}\\ \color{light} \bitbox{3}{} -\color{black} -\color{red} + + \bitbox{1}{1} \bitbox{1}{1} \bitbox{1}{1} -\color{black} + \bitbox{1}{0} \color{light} \bitbox[tbr]{18}{} @@ -869,7 +631,7 @@ the Requeue Stage for further details. A {\tt head} instruction marks the start of a loop; see the section on the Requeue Stage for further details. -\color{black} + \subsection{{\tt tail}} \newcommand{\bitsTail}{ \setlength{\bitwidth}{5mm} @@ -878,12 +640,12 @@ the Requeue Stage for further details. \bitheader[b]{18-21}\\ \color{light} \bitbox{3}{} -\color{black} -\color{red} + + \bitbox{1}{1} \bitbox{1}{1} \bitbox{1}{1} -\color{black} + \bitbox{1}{1} \color{light} \bitbox[tbr]{18}{} @@ -893,264 +655,20 @@ the Requeue Stage for further details. A {\tt tail} instruction marks the end of a loop; see the section on the Requeue Stage for further details. -\color{black} -%\pagebreak -%\subsection{{\tt takeOuterLoopCounter}} -% -%\setlength{\bitwidth}{5mm} -%{\tt -%\begin{bytefield}{25} -% \bitheader[b]{16-19,21}\\ -%\color{light} -% \bitbox{1}{A} -% \bitbox{1}{OS} -% \bitbox{2}{P} -%\color{black} -% \bitbox{3}{000} -% \bitbox{1}{0} -% \bitbox{2}{11} -%\color{light} -% \bitbox[tbr]{16}{} -%\color{black} -%\end{bytefield}} -% -%This instruction copies the value in the outer loop counter {\tt OLC} -%into the least significant bits of the data latch and leaves all other -%bits of the data latch unchanged. -% -%\subsection{{\tt takeInnerLoopCounter}} -% -%\setlength{\bitwidth}{5mm} -%{\tt -%\begin{bytefield}{25} -% \bitheader[b]{16-19,21}\\ -%\color{light} -% \bitbox{1}{A} -% \bitbox{1}{OS} -% \bitbox{2}{P} -%\color{black} -% \bitbox{3}{???} -% \bitbox{1}{?} -% \bitbox{2}{??} -%\color{light} -% \bitbox[tbr]{16}{} -%\color{black} -%\end{bytefield}} -% -%This instruction copies the value in the inner loop counter {\tt ILC} -%into the least significant bits of the data latch and leaves all other -%bits of the data latch unchanged. -% -% -% -%%\pagebreak -%%\subsection{{\tt interrupt}} -%% -%%\setlength{\bitwidth}{5mm} -%{\tt -%\begin{bytefield}{25} -% \bitheader[b]{0,5,16-19,21}\\ -%\color{light} -% \bitbox{4}{} -%\color{black} -% \bitbox{3}{000} -% \bitbox{1}{1} -% \bitbox{2}{00} -%\color{light} -% \bitbox[tbr]{16}{} -%\end{bytefield}} -% -%When an {\tt interrupt} instruction reaches {\tt IH}, it will wait -%there for the {\tt OD} stage to be full with an instruction that has -%the {\tt IM} bit set. When this occurs, the instruction at {\tt OD} -%{\it will not execute}, but {\it may reloop} if the conditions for -%relooping are met. -%\footnote{The ability to interrupt an instruction yet have it reloop is very -%useful for processing chunks of data with a fixed size header and/or -%footer and a variable length body.} -% -% -%\subsection{{\tt massacre}} -% -%\setlength{\bitwidth}{5mm} -%{\tt -%\begin{bytefield}{25} -% \bitheader[b]{16-19,21}\\ -%\color{light} -% \bitbox{4}{} -%\color{black} -% \bitbox{3}{000} -% \bitbox{1}{1} -% \bitbox{2}{01} -%\color{light} -% \bitbox[tbr]{16}{} -%\color{black} -%\end{bytefield}} -% -%When a {\tt massacre} instruction reaches {\tt IH}, it will wait there -%for the {\tt OD} stage to be full with an instruction that has the -%{\tt IM} bit set. When this occurs, all instructions in the -%instruction fifo (including {\tt OD}) are retired. -% -%\subsection{{\tt clog}} -% -%\setlength{\bitwidth}{5mm} -%{\tt -%\begin{bytefield}{25} -% \bitheader[b]{16-19,21}\\ -%\color{light} -% \bitbox{4}{} -%\color{black} -% \bitbox{3}{000} -% \bitbox{1}{1} -% \bitbox{2}{10} -%\color{light} -% \bitbox[tbr]{16}{} -%\color{black} -%\end{bytefield}} -% -%When a {\tt clog} instruction reaches {\tt OD}, it remains there and -%no more instructions will be executed until an {\tt unclog} is -%performed. -% -%\subsection{{\tt unclog}} -% -%\setlength{\bitwidth}{5mm} -%{\tt -%\begin{bytefield}{25} -% \bitheader[b]{16-19,21}\\ -%\color{light} -% \bitbox{4}{} -%\color{black} -% \bitbox{3}{000} -% \bitbox{1}{1} -% \bitbox[lrtb]{2}{11} -%\color{light} -% \bitbox[tbr]{16}{} -%\color{black} -%\end{bytefield}} -% -%When an {\tt unclog} instruction reaches {\tt IH}, it will wait there -%until a {\tt clog} instruction is at {\tt OD}. When this occurs, both -%instructions retire. -% -%Note that issuing an {\tt unclog} instruction to a dock which is not -%clogged and whose instruction fifo contains no {\tt clog} instructions -%will cause the dock to deadlock. - -\pagebreak -\section*{Marina Errata} - -The following additional restrictions have been imposed on the dock in -the Marina test chip: - -\subsection*{All Versions} - -\begin{enumerate} - -\item -A Marina dock initializes with the {\tt ILC}, {\tt OLC}, and flags in -an indeterminate state. - -\item -The instruction immediately after a {\tt move} instruction must not be -a {\tt set flags} instruction which utilizes the {\tt C}-flag (the -value of the {\tt C}-flag is not stable for a brief time after a {\tt - move}). - -\color{red} - -\item -If a {\tt move} instruction is torpedoable (ie it has the {\tt I} bit -set to {\tt 0}), it {\it must} have either the {\tt Ti} bit or {\tt - Di} bit set (or both). It is not permitted for a torpedoable {\tt - move} to have both bits cleared. - -\color{black} - -\end{enumerate} - - -\subsection*{Marina with Ivan's Counter} - -\begin{enumerate} - -\item - -A torpedoable {\tt move} instruction must not be followed immediately -by a {\tt set olc} instruction or another torpedoable {\tt move}. - -\item - -This document specifies that when a torpedoable {\tt move} instruction -executes successfully, the \color{red}{\tt Z}\color{black} flag is unchanged. In Marina, when -a torpedoable {\tt move} instruction executes successfully, it causes -the \color{red}{\tt Z}\color{black} flag to be set if the {\tt OLC} was zero and causes it to -be cleared if the {\tt OLC} was nonzero. Thus, in the following -instruction sequence: - - \begin{verbatim} - head; - [*] set olc=1; - send token to self:i; - [T] recv token; - [*] send token to self; - [T] recv token; - [*] abort; - tail; - \end{verbatim} - -Will leave the \color{red}{\tt Z}\color{black} flag {\it set} on Marina, whereas a strict -implementation of this document would leave it cleared. - -In practice, this distinction rarely matters. - -\end{enumerate} - -\subsection*{Marina with Kessels Counter} - -With the Kessels counter, the \color{red}{\tt Z}\color{black}-flag {\it is exactly equal to} -the zeroness of the {\tt OLC}; it cannot be ``out of sync'' with it. - -\begin{enumerate} - -\item -Every ``load OLC'' instruction must be predicated on the \color{red}{\tt Z}\color{black}-flag -being {\it set}. This is a sneaky way of forcing the programmer to -``run down'' the counter before loading it, because Kessels' counter -does not support ``unloading.'' - -\item -Every ``decrement OLC'' instruction must be predicated on the {\tt - D}-flag being {\it cleared}. This way we never have to check if the -counter is already empty before decrementing. - -\item -The instruction after a torpedoable {\tt move} must not be predicated -on the \color{red}{\tt Z}\color{black}-flag being {\it set} (it may be predicated on the {\tt - D}-flag being {\it cleared}. This is because, while the move -instruction is waiting to execute, the \color{red}{\tt Z}\color{black}-flag will be cleared, -and the predicate stage believes that it can skip the instruction even -though {\tt do[ins]} is still high (I think this is dumb). - - -\end{enumerate} - -\color{black} - +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \pagebreak -\section*{Instruction Encoding Map\color{black}} +\section*{Instruction Encoding Map} \vspace{3mm}\hspace{-1cm}{\tt move}\hspace{1cm}\vspace{-6mm}\\ -\bitsMove +%\bitsMove \bitsFlush \vspace{3mm}\hspace{-1cm}{\tt shift}\hspace{1cm}\vspace{-6mm}\\ \bitsShift \vspace{3mm}\hspace{-1cm}{\tt set}\hspace{1cm}\vspace{-6mm}\\ -\bitsSet +%\bitsSet \vspace{3mm}\hspace{-1cm}{\tt abort}\hspace{1cm}\vspace{-6mm}\\ \bitsAbort @@ -1162,23 +680,4 @@ though {\tt do[ins]} is still high (I think this is dumb). \bitsTail -%\pagebreak -%\epsfig{file=all,height=5in,angle=90} - -%\pagebreak -%\subsection*{Input Dock} -%\epsfig{file=in,width=8in,angle=90} - -%\pagebreak -%\subsection*{Output Dock} -%\epsfig{file=out,width=8in,angle=90} - - -%\pagebreak -%\epsfig{file=ports,height=5in,angle=90} - -%\pagebreak -%\epsfig{file=best,height=5in,angle=90} - - \end{document} -- 1.7.10.4