1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Size(..), intSize, floatSize, isFloatSize,
29 wordSize, cmmTypeSize, sizeToWidth,
32 Imm(..), strImmLit, litToImm,
40 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
41 RegClass(..), regClass,
47 get_GlobalReg_reg_or_addr,
49 -- * Machine-dependent register-related stuff
50 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
51 allocatableRegsInClass,
58 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
61 EABase(..), EAIndex(..),
62 eax, ebx, ecx, edx, esi, edi, ebp, esp,
63 fake0, fake1, fake2, fake3, fake4, fake5,
66 #if x86_64_TARGET_ARCH
67 EABase(..), EAIndex(..), ripRel,
68 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
69 eax, ebx, ecx, edx, esi, edi, ebp, esp,
70 r8, r9, r10, r11, r12, r13, r14, r15,
71 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
72 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
74 addrModeRegs, allFPArgRegs,
78 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
79 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
81 #if powerpc_TARGET_ARCH
90 #include "HsVersions.h"
93 # define STOLEN_X86_REGS 4
94 -- HACK: go for the max
97 #include "../includes/MachRegs.h"
100 import CgUtils ( get_GlobalReg_addr )
101 import CLabel ( CLabel, mkMainCapabilityLabel )
103 import Outputable ( Outputable(..), pprPanic, panic )
104 import qualified Outputable
112 #if powerpc_TARGET_ARCH
113 import Data.Word ( Word8, Word16, Word32 )
114 import Data.Int ( Int8, Int16, Int32 )
117 -- -----------------------------------------------------------------------------
118 -- Sizes on this architecture
120 -- A Size is usually a combination of width and class
122 -- It looks very like the old MachRep, but it's now of purely local
123 -- significance, here in the native code generator. You can change it
124 -- without global consequences.
126 -- A major use is as an opcode qualifier; thus the opcode
130 -- where the Size field encodes the ".l" part.
132 -- ToDo: it's not clear to me that we need separate signed-vs-unsigned sizes
133 -- here. I've removed them from the x86 version, we'll see what happens --SDM
135 -- ToDo: quite a few occurrences of Size could usefully be replaced by Width
137 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
138 data Size -- For these three, the "size" also gives the int/float
139 -- distinction, because the instructions for int/float
140 -- differ only in their suffices
141 = II8 | II16 | II32 | II64 | FF32 | FF64 | FF80
144 intSize, floatSize :: Width -> Size
149 intSize other = pprPanic "MachInstrs.intSize" (ppr other)
153 floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
156 wordSize = intSize wordWidth
158 sizeToWidth :: Size -> Width
160 sizeToWidth II16 = W16
161 sizeToWidth II32 = W32
162 sizeToWidth II64 = W64
163 sizeToWidth FF32 = W32
164 sizeToWidth FF64 = W64
165 sizeToWidth _ = panic "MachInstrs.sizeToWidth"
167 cmmTypeSize :: CmmType -> Size
168 cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
169 | otherwise = intSize (typeWidth ty)
171 isFloatSize :: Size -> Bool
172 isFloatSize FF32 = True
173 isFloatSize FF64 = True
174 isFloatSize FF80 = True
175 isFloatSize other = False
178 #if alpha_TARGET_ARCH
182 -- | W -- word (2 bytes): UNUSED
184 | L -- longword (4 bytes)
185 | Q -- quadword (8 bytes)
186 -- | FF -- VAX F-style floating pt: UNUSED
187 -- | GF -- VAX G-style floating pt: UNUSED
188 -- | DF -- VAX D-style floating pt: UNUSED
189 -- | SF -- IEEE single-precision floating pt: UNUSED
190 | TF -- IEEE double-precision floating pt
194 #if sparc_TARGET_ARCH /* || powerpc_TARGET_ARCH */
197 | Bu -- byte (unsigned)
198 | H -- halfword (signed, 2 bytes)
199 | Hu -- halfword (unsigned, 2 bytes)
200 | W -- word (4 bytes)
201 | F -- IEEE single-precision floating pt
202 | DF -- IEEE single-precision floating pt
206 -- -----------------------------------------------------------------------------
211 | ImmInteger Integer -- Sigh.
212 | ImmCLbl CLabel -- AbstractC Label (with baggage)
213 | ImmLit Doc -- Simple string
214 | ImmIndex CLabel Int
217 | ImmConstantSum Imm Imm
218 | ImmConstantDiff Imm Imm
219 #if sparc_TARGET_ARCH
220 | LO Imm {- Possible restrictions... -}
223 #if powerpc_TARGET_ARCH
226 | HA Imm {- high halfword adjusted -}
228 strImmLit s = ImmLit (text s)
230 litToImm :: CmmLit -> Imm
231 litToImm (CmmInt i _) = ImmInteger i
232 litToImm (CmmFloat f W32) = ImmFloat f
233 litToImm (CmmFloat f W64) = ImmDouble f
234 litToImm (CmmLabel l) = ImmCLbl l
235 litToImm (CmmLabelOff l off) = ImmIndex l off
236 litToImm (CmmLabelDiffOff l1 l2 off)
238 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
241 -- -----------------------------------------------------------------------------
245 #if alpha_TARGET_ARCH
251 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
252 = AddrBaseIndex EABase EAIndex Displacement
255 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
256 data EAIndex = EAIndexNone | EAIndex Reg Int
257 type Displacement = Imm
260 #if sparc_TARGET_ARCH
265 #if powerpc_TARGET_ARCH
270 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
271 addrModeRegs :: AddrMode -> [Reg]
272 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
274 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
275 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
280 addrOffset :: AddrMode -> Int -> Maybe AddrMode
284 #if alpha_TARGET_ARCH
285 _ -> panic "MachMisc.addrOffset not defined for Alpha"
287 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
288 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
290 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
291 AddrBaseIndex r i (ImmInteger n)
292 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
294 AddrBaseIndex r i (ImmCLbl lbl)
295 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
297 AddrBaseIndex r i (ImmIndex lbl ix)
298 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
300 _ -> Nothing -- in theory, shouldn't happen
302 #if sparc_TARGET_ARCH
303 AddrRegImm r (ImmInt n)
304 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
305 | otherwise -> Nothing
308 AddrRegImm r (ImmInteger n)
309 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
310 | otherwise -> Nothing
311 where n2 = n + toInteger off
313 AddrRegReg r (RealReg 0)
314 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
315 | otherwise -> Nothing
319 #if powerpc_TARGET_ARCH
320 AddrRegImm r (ImmInt n)
321 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
322 | otherwise -> Nothing
325 AddrRegImm r (ImmInteger n)
326 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
327 | otherwise -> Nothing
328 where n2 = n + toInteger off
334 #if alpha_TARGET_ARCH
336 fits8Bits :: Integer -> Bool
337 fits8Bits i = i >= -256 && i < 256
341 #if sparc_TARGET_ARCH
343 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
344 fits13Bits :: Integral a => a -> Bool
345 fits13Bits x = x >= -4096 && x < 4096
349 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
350 ++show i++");\nprobably because of large constant data structures;" ++
351 "\nworkaround: use -fvia-C on this module.\n")
355 #if powerpc_TARGET_ARCH
356 fits16Bits :: Integral a => a -> Bool
357 fits16Bits x = x >= -32768 && x < 32768
359 makeImmediate :: Integral a => Width -> Bool -> a -> Maybe Imm
360 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
362 narrow W32 False = fromIntegral (fromIntegral x :: Word32)
363 narrow W16 False = fromIntegral (fromIntegral x :: Word16)
364 narrow W8 False = fromIntegral (fromIntegral x :: Word8)
365 narrow W32 True = fromIntegral (fromIntegral x :: Int32)
366 narrow W16 True = fromIntegral (fromIntegral x :: Int16)
367 narrow W8 True = fromIntegral (fromIntegral x :: Int8)
369 narrowed = narrow rep signed
372 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
373 | otherwise = Nothing
375 | narrowed >= 0 && narrowed < 65536 = Just narrowed
376 | otherwise = Nothing
377 toI16 _ _ = Just narrowed
381 -- @spRel@ gives us a stack relative addressing mode for volatile
382 -- temporaries and for excess call arguments. @fpRel@, where
383 -- applicable, is the same but for the frame pointer.
385 spRel :: Int -- desired stack offset in words, positive or negative
389 #if defined(i386_TARGET_ARCH)
390 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
391 #elif defined(x86_64_TARGET_ARCH)
392 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
394 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
397 #if sparc_TARGET_ARCH
398 fpRel :: Int -> AddrMode
399 -- Duznae work for offsets greater than 13 bits; we just hope for
402 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
405 #if x86_64_TARGET_ARCH
406 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
409 -- -----------------------------------------------------------------------------
412 -- We map STG registers onto appropriate CmmExprs. Either they map
413 -- to real machine registers or stored as offsets from BaseReg. Given
414 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
415 -- register it is in, on this platform, or a CmmExpr denoting the
416 -- address in the register table holding it.
417 -- (See also get_GlobalReg_addr in CgUtils.)
419 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
420 get_GlobalReg_reg_or_addr mid
421 = case globalRegMaybe mid of
423 Nothing -> Right (get_GlobalReg_addr mid)
425 -- ---------------------------------------------------------------------------
428 -- RealRegs are machine regs which are available for allocation, in
429 -- the usual way. We know what class they are, because that's part of
430 -- the processor's architecture.
432 -- VirtualRegs are virtual registers. The register allocator will
433 -- eventually have to map them into RealRegs, or into spill slots.
434 -- VirtualRegs are allocated on the fly, usually to represent a single
435 -- value in the abstract assembly code (i.e. dynamic registers are
436 -- usually single assignment). With the new register allocator, the
437 -- single assignment restriction isn't necessary to get correct code,
438 -- although a better register allocation will result if single
439 -- assignment is used -- because the allocator maps a VirtualReg into
440 -- a single RealReg, even if the VirtualReg has multiple live ranges.
442 -- Virtual regs can be of either class, so that info is attached.
444 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
445 -- when supplied with the vreg for the lower-half of the quantity.
446 -- (NB. Not reversible).
447 getHiVRegFromLo (VirtualRegI u)
448 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
449 getHiVRegFromLo other
450 = pprPanic "getHiVRegFromLo" (ppr other)
458 instance Uniquable RegClass where
459 getUnique RcInteger = mkUnique 'L' 0
460 getUnique RcFloat = mkUnique 'L' 1
461 getUnique RcDouble = mkUnique 'L' 2
466 = RealReg {-# UNPACK #-} !RegNo
467 | VirtualRegI {-# UNPACK #-} !Unique
468 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
469 | VirtualRegF {-# UNPACK #-} !Unique
470 | VirtualRegD {-# UNPACK #-} !Unique
473 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
474 -- in the register allocator.
475 instance Uniquable Reg where
476 getUnique (RealReg i) = mkUnique 'C' i
477 getUnique (VirtualRegI u) = u
478 getUnique (VirtualRegHi u) = u
479 getUnique (VirtualRegF u) = u
480 getUnique (VirtualRegD u) = u
482 unRealReg (RealReg i) = i
483 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
485 mkVReg :: Unique -> Size -> Reg
487 | not (isFloatSize size) = VirtualRegI u
490 #if sparc_TARGET_ARCH
491 FF32 -> VirtualRegF u
493 FF32 -> VirtualRegD u
495 FF64 -> VirtualRegD u
496 _other -> panic "mkVReg"
498 isVirtualReg :: Reg -> Bool
499 isVirtualReg (RealReg _) = False
500 isVirtualReg (VirtualRegI _) = True
501 isVirtualReg (VirtualRegHi _) = True
502 isVirtualReg (VirtualRegF _) = True
503 isVirtualReg (VirtualRegD _) = True
505 isRealReg :: Reg -> Bool
506 isRealReg = not . isVirtualReg
508 renameVirtualReg :: Unique -> Reg -> Reg
511 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
512 VirtualRegI _ -> VirtualRegI u
513 VirtualRegHi _ -> VirtualRegHi u
514 VirtualRegF _ -> VirtualRegF u
515 VirtualRegD _ -> VirtualRegD u
517 instance Show Reg where
518 show (RealReg i) = showReg i
519 show (VirtualRegI u) = "%vI_" ++ show u
520 show (VirtualRegHi u) = "%vHi_" ++ show u
521 show (VirtualRegF u) = "%vF_" ++ show u
522 show (VirtualRegD u) = "%vD_" ++ show u
524 instance Outputable RegClass where
525 ppr RcInteger = Outputable.text "I"
526 ppr RcFloat = Outputable.text "F"
527 ppr RcDouble = Outputable.text "D"
529 instance Outputable Reg where
530 ppr r = Outputable.text (show r)
535 -- trivColorable function for the graph coloring allocator
536 -- This gets hammered by scanGraph during register allocation,
537 -- so needs to be fairly efficient.
539 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
540 -- (which are disjoint) ie. x86, x86_64 and ppc
544 -- Doing a nice fold over the UniqSet makes trivColorable use
545 -- 32% of total compile time and 42% of total alloc when compiling SHA1.lhs from darcs.
547 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
548 trivColorable classN conflicts exclusions
551 acc :: Reg -> (Int, Int) -> (Int, Int)
554 RcInteger -> (cd+1, cf)
555 RcDouble -> (cd, cf+1)
556 _ -> panic "MachRegs.trivColorable: reg class not handled"
558 tmp = foldUniqSet acc (0, 0) conflicts
559 (countInt, countFloat) = foldUniqSet acc tmp exclusions
561 squeese = worst countInt classN RcInteger
562 + worst countFloat classN RcDouble
564 in squeese < allocatableRegsInClass classN
566 -- | Worst case displacement
567 -- node N of classN has n neighbors of class C.
569 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
570 -- This is a bit boring compared to what's in RegArchX86.
572 worst :: Int -> RegClass -> RegClass -> Int
573 worst n classN classC
577 RcInteger -> min n (allocatableRegsInClass RcInteger)
582 RcDouble -> min n (allocatableRegsInClass RcDouble)
587 -- The number of allocatable regs is hard coded here so we can do a fast comparision
588 -- in trivColorable. It's ok if these numbers are _less_ than the actual number of
589 -- free regs, but they can't be more or the register conflict graph won't color.
591 -- There is an allocatableRegsInClass :: RegClass -> Int, but doing the unboxing
592 -- is too slow for us here.
594 -- Compare MachRegs.freeRegs and MachRegs.h to get these numbers.
597 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
598 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
600 #elif x86_64_TARGET_ARCH
601 #define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
602 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(2))
604 #elif powerpc_TARGET_ARCH
605 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
606 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(26))
609 #error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
612 {-# INLINE regClass #-}
613 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
614 trivColorable classN conflicts exclusions
615 = {-# SCC "trivColorable" #-}
617 {-# INLINE isSqueesed #-}
620 NodeUFM _ _ left right
621 -> case isSqueesed cI cF right of
624 False -> isSqueesed cI' cF' left
625 True -> (# True, cI', cF' #)
628 -> case regClass reg of
630 -> case cI +# _ILIT(1) of
631 cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
634 -> case cF +# _ILIT(1) of
635 cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE, cI, cF' #)
638 -> (# False, cI, cF #)
640 in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
641 (# False, cI', cF' #)
642 -> case isSqueesed cI' cF' exclusions of
643 (# s, _, _ #) -> not s
650 -- -----------------------------------------------------------------------------
651 -- Machine-specific register stuff
653 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
654 -- point registers. The mapping of STG registers to alpha machine registers
655 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
657 #if alpha_TARGET_ARCH
661 v0, f0, ra, pv, gp, sp, zeroh :: Reg
663 f0 = realReg (fReg 0)
664 ra = FixedReg ILIT(26)
666 gp = FixedReg ILIT(29)
667 sp = FixedReg ILIT(30)
668 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
670 t9, t10, t11, t12 :: Reg
678 Intel x86 architecture:
679 - All registers except 7 (esp) are available for use.
680 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
681 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
682 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
683 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
684 fp registers, and 3-operand insns for them, and we translate this into
685 real stack-based x86 fp code after register allocation.
687 The fp registers are all Double registers; we don't have any RcFloat class
688 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
694 fake0, fake1, fake2, fake3, fake4, fake5,
695 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
712 -- On x86, we might want to have an 8-bit RegClass, which would
713 -- contain just regs 1-4 (the others don't have 8-bit versions).
714 -- However, we can get away without this at the moment because the
715 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
716 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
717 regClass (VirtualRegI u) = RcInteger
718 regClass (VirtualRegHi u) = RcInteger
719 regClass (VirtualRegD u) = RcDouble
720 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
721 (ppr (VirtualRegF u))
724 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
725 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
727 showReg :: RegNo -> String
729 = if n >= 0 && n < 14
731 else "%unknown_x86_real_reg_" ++ show n
737 AMD x86_64 architecture:
738 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
739 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
740 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
744 #if x86_64_TARGET_ARCH
746 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
747 r8, r9, r10, r11, r12, r13, r14, r15,
748 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
749 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
784 -- so we can re-use some x86 code:
794 xmm n = RealReg (16+n)
796 -- On x86, we might want to have an 8-bit RegClass, which would
797 -- contain just regs 1-4 (the others don't have 8-bit versions).
798 -- However, we can get away without this at the moment because the
799 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
800 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
801 regClass (VirtualRegI u) = RcInteger
802 regClass (VirtualRegHi u) = RcInteger
803 regClass (VirtualRegD u) = RcDouble
804 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
805 (ppr (VirtualRegF u))
808 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
810 showReg :: RegNo -> String
812 | n >= 16 = "%xmm" ++ show (n-16)
813 | n >= 8 = "%r" ++ show n
814 | otherwise = regNames !! n
819 The SPARC has 64 registers of interest; 32 integer registers and 32
820 floating point registers. The mapping of STG registers to SPARC
821 machine registers is defined in StgRegs.h. We are, of course,
822 prepared for any eventuality.
824 The whole fp-register pairing thing on sparcs is a huge nuisance. See
825 fptools/ghc/includes/MachRegs.h for a description of what's going on
829 #if sparc_TARGET_ARCH
831 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
838 nCG_FirstFloatReg :: RegNo
839 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
841 regClass (VirtualRegI u) = RcInteger
842 regClass (VirtualRegF u) = RcFloat
843 regClass (VirtualRegD u) = RcDouble
844 regClass (RealReg i) | i < 32 = RcInteger
845 | i < nCG_FirstFloatReg = RcDouble
846 | otherwise = RcFloat
848 showReg :: RegNo -> String
850 | n >= 0 && n < 8 = "%g" ++ show n
851 | n >= 8 && n < 16 = "%o" ++ show (n-8)
852 | n >= 16 && n < 24 = "%l" ++ show (n-16)
853 | n >= 24 && n < 32 = "%i" ++ show (n-24)
854 | n >= 32 && n < 64 = "%f" ++ show (n-32)
855 | otherwise = "%unknown_sparc_real_reg_" ++ show n
857 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
859 f6 = RealReg (fReg 6)
860 f8 = RealReg (fReg 8)
861 f22 = RealReg (fReg 22)
862 f26 = RealReg (fReg 26)
863 f27 = RealReg (fReg 27)
866 -- g0 is useful for codegen; is always zero, and writes to it vanish.
867 g0 = RealReg (gReg 0)
868 g1 = RealReg (gReg 1)
869 g2 = RealReg (gReg 2)
871 -- FP, SP, int and float return (from C) regs.
872 fp = RealReg (iReg 6)
873 sp = RealReg (oReg 6)
874 o0 = RealReg (oReg 0)
875 o1 = RealReg (oReg 1)
876 f0 = RealReg (fReg 0)
877 f1 = RealReg (fReg 1)
882 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
886 #if powerpc_TARGET_ARCH
890 regClass (VirtualRegI u) = RcInteger
891 regClass (VirtualRegHi u) = RcInteger
892 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
893 (ppr (VirtualRegF u))
894 regClass (VirtualRegD u) = RcDouble
895 regClass (RealReg i) | i < 32 = RcInteger
896 | otherwise = RcDouble
898 showReg :: RegNo -> String
900 | n >= 0 && n <= 31 = "%r" ++ show n
901 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
902 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
909 f1 = RealReg $ fReg 1
910 f20 = RealReg $ fReg 20
911 f21 = RealReg $ fReg 21
915 Redefine the literals used for machine-registers with non-numeric
916 names in the header files. Gag me with a spoon, eh?
919 #if alpha_TARGET_ARCH
970 #if x86_64_TARGET_ARCH
1005 #if sparc_TARGET_ARCH
1073 #if powerpc_TARGET_ARCH
1107 #ifdef darwin_TARGET_OS
1177 -- allMachRegs is the complete set of machine regs.
1178 allMachRegNos :: [RegNo]
1180 = IF_ARCH_alpha( [0..63],
1181 IF_ARCH_i386( [0..13],
1182 IF_ARCH_x86_64( [0..31],
1183 IF_ARCH_sparc( ([0..31]
1184 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1185 ++ [nCG_FirstFloatReg .. f31]),
1186 IF_ARCH_powerpc([0..63],
1189 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1190 -- i.e., these are the regs for which we are prepared to allow the
1191 -- register allocator to attempt to map VRegs to.
1192 allocatableRegs :: [RegNo]
1194 = let isFree i = isFastTrue (freeReg i)
1195 in filter isFree allMachRegNos
1198 -- | The number of regs in each class.
1199 -- We go via top level CAFs to ensure that we're not recomputing
1200 -- the length of these lists each time the fn is called.
1201 allocatableRegsInClass :: RegClass -> Int
1202 allocatableRegsInClass cls
1204 RcInteger -> allocatableRegsInteger
1205 RcDouble -> allocatableRegsDouble
1207 allocatableRegsInteger
1208 = length $ filter (\r -> regClass r == RcInteger)
1209 $ map RealReg allocatableRegs
1211 allocatableRegsDouble
1212 = length $ filter (\r -> regClass r == RcDouble)
1213 $ map RealReg allocatableRegs
1216 -- these are the regs which we cannot assume stay alive over a
1218 callClobberedRegs :: [Reg]
1221 #if alpha_TARGET_ARCH
1222 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1223 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1224 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1225 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1226 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1227 #endif /* alpha_TARGET_ARCH */
1228 #if i386_TARGET_ARCH
1229 -- caller-saves registers
1230 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1231 #endif /* i386_TARGET_ARCH */
1232 #if x86_64_TARGET_ARCH
1233 -- caller-saves registers
1234 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1235 -- all xmm regs are caller-saves
1236 #endif /* x86_64_TARGET_ARCH */
1237 #if sparc_TARGET_ARCH
1240 [oReg i | i <- [0..5]] ++
1241 [gReg i | i <- [1..7]] ++
1242 [fReg i | i <- [0..31]] )
1243 #endif /* sparc_TARGET_ARCH */
1244 #if powerpc_TARGET_ARCH
1245 #if darwin_TARGET_OS
1246 map RealReg (0:[2..12] ++ map fReg [0..13])
1247 #elif linux_TARGET_OS
1248 map RealReg (0:[2..13] ++ map fReg [0..13])
1250 #endif /* powerpc_TARGET_ARCH */
1253 -- argRegs is the set of regs which are read for an n-argument call to C.
1254 -- For archs which pass all args on the stack (x86), is empty.
1255 -- Sparc passes up to the first 6 args in regs.
1256 -- Dunno about Alpha.
1257 argRegs :: RegNo -> [Reg]
1259 #if i386_TARGET_ARCH
1260 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1263 #if x86_64_TARGET_ARCH
1264 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1267 #if alpha_TARGET_ARCH
1269 argRegs 1 = freeMappedRegs [16, fReg 16]
1270 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1271 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1272 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1273 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1274 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1275 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1276 #endif /* alpha_TARGET_ARCH */
1278 #if sparc_TARGET_ARCH
1280 argRegs 1 = map (RealReg . oReg) [0]
1281 argRegs 2 = map (RealReg . oReg) [0,1]
1282 argRegs 3 = map (RealReg . oReg) [0,1,2]
1283 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1284 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1285 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1286 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1287 #endif /* sparc_TARGET_ARCH */
1289 #if powerpc_TARGET_ARCH
1291 argRegs 1 = map RealReg [3]
1292 argRegs 2 = map RealReg [3,4]
1293 argRegs 3 = map RealReg [3..5]
1294 argRegs 4 = map RealReg [3..6]
1295 argRegs 5 = map RealReg [3..7]
1296 argRegs 6 = map RealReg [3..8]
1297 argRegs 7 = map RealReg [3..9]
1298 argRegs 8 = map RealReg [3..10]
1299 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1300 #endif /* powerpc_TARGET_ARCH */
1303 -- all of the arg regs ??
1304 #if alpha_TARGET_ARCH
1305 allArgRegs :: [(Reg, Reg)]
1306 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1307 #endif /* alpha_TARGET_ARCH */
1309 #if sparc_TARGET_ARCH
1311 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1312 #endif /* sparc_TARGET_ARCH */
1314 #if i386_TARGET_ARCH
1316 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1319 #if x86_64_TARGET_ARCH
1321 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1322 allFPArgRegs :: [Reg]
1323 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1326 #if powerpc_TARGET_ARCH
1328 allArgRegs = map RealReg [3..10]
1329 allFPArgRegs :: [Reg]
1330 #if darwin_TARGET_OS
1331 allFPArgRegs = map (RealReg . fReg) [1..13]
1332 #elif linux_TARGET_OS
1333 allFPArgRegs = map (RealReg . fReg) [1..8]
1335 #endif /* powerpc_TARGET_ARCH */
1339 freeReg :: RegNo -> FastBool
1341 #if alpha_TARGET_ARCH
1342 freeReg 26 = fastBool False -- return address (ra)
1343 freeReg 28 = fastBool False -- reserved for the assembler (at)
1344 freeReg 29 = fastBool False -- global pointer (gp)
1345 freeReg 30 = fastBool False -- stack pointer (sp)
1346 freeReg 31 = fastBool False -- always zero (zeroh)
1347 freeReg 63 = fastBool False -- always zero (f31)
1350 #if i386_TARGET_ARCH
1351 freeReg esp = fastBool False -- %esp is the C stack pointer
1354 #if x86_64_TARGET_ARCH
1355 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1358 #if sparc_TARGET_ARCH
1359 freeReg g0 = fastBool False -- %g0 is always 0.
1360 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1361 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1362 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1363 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1364 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1365 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1366 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1367 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1368 freeReg f1 = fastBool False
1371 #if powerpc_TARGET_ARCH
1372 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1373 freeReg 1 = fastBool False -- The Stack Pointer
1374 #if !darwin_TARGET_OS
1375 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1376 freeReg 2 = fastBool False
1381 freeReg REG_Base = fastBool False
1384 freeReg REG_R1 = fastBool False
1387 freeReg REG_R2 = fastBool False
1390 freeReg REG_R3 = fastBool False
1393 freeReg REG_R4 = fastBool False
1396 freeReg REG_R5 = fastBool False
1399 freeReg REG_R6 = fastBool False
1402 freeReg REG_R7 = fastBool False
1405 freeReg REG_R8 = fastBool False
1408 freeReg REG_F1 = fastBool False
1411 freeReg REG_F2 = fastBool False
1414 freeReg REG_F3 = fastBool False
1417 freeReg REG_F4 = fastBool False
1420 freeReg REG_D1 = fastBool False
1423 freeReg REG_D2 = fastBool False
1426 freeReg REG_Sp = fastBool False
1429 freeReg REG_Su = fastBool False
1432 freeReg REG_SpLim = fastBool False
1435 freeReg REG_Hp = fastBool False
1438 freeReg REG_HpLim = fastBool False
1440 freeReg n = fastBool True
1443 -- | Returns 'Nothing' if this global register is not stored
1444 -- in a real machine register, otherwise returns @'Just' reg@, where
1445 -- reg is the machine register it is stored in.
1447 globalRegMaybe :: GlobalReg -> Maybe Reg
1450 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1453 globalRegMaybe (VanillaReg 1 _) = Just (RealReg REG_R1)
1456 globalRegMaybe (VanillaReg 2 _) = Just (RealReg REG_R2)
1459 globalRegMaybe (VanillaReg 3 _) = Just (RealReg REG_R3)
1462 globalRegMaybe (VanillaReg 4 _) = Just (RealReg REG_R4)
1465 globalRegMaybe (VanillaReg 5 _) = Just (RealReg REG_R5)
1468 globalRegMaybe (VanillaReg 6 _) = Just (RealReg REG_R6)
1471 globalRegMaybe (VanillaReg 7 _) = Just (RealReg REG_R7)
1474 globalRegMaybe (VanillaReg 8 _) = Just (RealReg REG_R8)
1477 globalRegMaybe (VanillaReg 9 _) = Just (RealReg REG_R9)
1480 globalRegMaybe (VanillaReg 10 _) = Just (RealReg REG_R10)
1483 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1486 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1489 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1492 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1495 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1498 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1501 globalRegMaybe Sp = Just (RealReg REG_Sp)
1504 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1507 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1510 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1513 globalRegMaybe Hp = Just (RealReg REG_Hp)
1516 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1518 #ifdef REG_CurrentTSO
1519 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1521 #ifdef REG_CurrentNursery
1522 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1524 globalRegMaybe _ = Nothing