1 -- -----------------------------------------------------------------------------
3 -- (c) The University of Glasgow 1994-2004
5 -- Machine-specific info about registers.
7 -- Also includes stuff about immediate operands, which are
8 -- often/usually quite entangled with registers.
10 -- (Immediates could be untangled from registers at some cost in tangled
11 -- modules --- the pleasure has been foregone.)
13 -- -----------------------------------------------------------------------------
17 -- The above warning supression flag is a temporary kludge.
18 -- While working on this module you are encouraged to remove it and fix
19 -- any warnings in the module. See
20 -- http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
23 #include "nativeGen/NCG.h"
28 Size(..), intSize, floatSize, isFloatSize,
29 wordSize, cmmTypeSize, sizeToWidth,
32 Imm(..), strImmLit, litToImm,
40 Reg(..), isRealReg, isVirtualReg, renameVirtualReg,
41 RegClass(..), regClass,
47 get_GlobalReg_reg_or_addr,
49 -- * Machine-dependent register-related stuff
50 allocatableRegs, argRegs, allArgRegs, callClobberedRegs,
51 allocatableRegsInClass,
58 gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh,
61 EABase(..), EAIndex(..),
62 eax, ebx, ecx, edx, esi, edi, ebp, esp,
63 fake0, fake1, fake2, fake3, fake4, fake5,
66 #if x86_64_TARGET_ARCH
67 EABase(..), EAIndex(..), ripRel,
68 rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp,
69 eax, ebx, ecx, edx, esi, edi, ebp, esp,
70 r8, r9, r10, r11, r12, r13, r14, r15,
71 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
72 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
74 addrModeRegs, allFPArgRegs,
78 fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
79 fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
81 #if powerpc_TARGET_ARCH
90 #include "HsVersions.h"
93 # define STOLEN_X86_REGS 4
94 -- HACK: go for the max
97 #include "../includes/MachRegs.h"
101 import CgUtils ( get_GlobalReg_addr )
102 import CLabel ( CLabel, mkMainCapabilityLabel )
104 import Outputable ( Outputable(..), pprPanic, panic )
105 import qualified Outputable
113 #if powerpc_TARGET_ARCH
114 import Data.Word ( Word8, Word16, Word32 )
115 import Data.Int ( Int8, Int16, Int32 )
118 -- -----------------------------------------------------------------------------
119 -- Sizes on this architecture
121 -- A Size is usually a combination of width and class
123 -- It looks very like the old MachRep, but it's now of purely local
124 -- significance, here in the native code generator. You can change it
125 -- without global consequences.
127 -- A major use is as an opcode qualifier; thus the opcode
131 -- where the Size field encodes the ".l" part.
133 -- ToDo: it's not clear to me that we need separate signed-vs-unsigned sizes
134 -- here. I've removed them from the x86 version, we'll see what happens --SDM
136 -- ToDo: quite a few occurrences of Size could usefully be replaced by Width
138 #if powerpc_TARGET_ARCH || i386_TARGET_ARCH || x86_64_TARGET_ARCH
139 data Size -- For these three, the "size" also gives the int/float
140 -- distinction, because the instructions for int/float
141 -- differ only in their suffices
142 = II8 | II16 | II32 | II64 | FF32 | FF64 | FF80
145 intSize, floatSize :: Width -> Size
150 intSize other = pprPanic "MachInstrs.intSize" (ppr other)
154 floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
157 wordSize = intSize wordWidth
159 sizeToWidth :: Size -> Width
161 sizeToWidth II16 = W16
162 sizeToWidth II32 = W32
163 sizeToWidth II64 = W64
164 sizeToWidth FF32 = W32
165 sizeToWidth FF64 = W64
166 sizeToWidth _ = panic "MachInstrs.sizeToWidth"
168 cmmTypeSize :: CmmType -> Size
169 cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
170 | otherwise = intSize (typeWidth ty)
172 isFloatSize :: Size -> Bool
173 isFloatSize FF32 = True
174 isFloatSize FF64 = True
175 isFloatSize FF80 = True
176 isFloatSize other = False
179 #if alpha_TARGET_ARCH
183 -- | W -- word (2 bytes): UNUSED
185 | L -- longword (4 bytes)
186 | Q -- quadword (8 bytes)
187 -- | FF -- VAX F-style floating pt: UNUSED
188 -- | GF -- VAX G-style floating pt: UNUSED
189 -- | DF -- VAX D-style floating pt: UNUSED
190 -- | SF -- IEEE single-precision floating pt: UNUSED
191 | TF -- IEEE double-precision floating pt
195 #if sparc_TARGET_ARCH /* || powerpc_TARGET_ARCH */
198 | Bu -- byte (unsigned)
199 | H -- halfword (signed, 2 bytes)
200 | Hu -- halfword (unsigned, 2 bytes)
201 | W -- word (4 bytes)
202 | F -- IEEE single-precision floating pt
203 | DF -- IEEE single-precision floating pt
207 -- -----------------------------------------------------------------------------
212 | ImmInteger Integer -- Sigh.
213 | ImmCLbl CLabel -- AbstractC Label (with baggage)
214 | ImmLit Doc -- Simple string
215 | ImmIndex CLabel Int
218 | ImmConstantSum Imm Imm
219 | ImmConstantDiff Imm Imm
220 #if sparc_TARGET_ARCH
221 | LO Imm {- Possible restrictions... -}
224 #if powerpc_TARGET_ARCH
227 | HA Imm {- high halfword adjusted -}
229 strImmLit s = ImmLit (text s)
231 litToImm :: CmmLit -> Imm
232 litToImm (CmmInt i _) = ImmInteger i
233 litToImm (CmmFloat f W32) = ImmFloat f
234 litToImm (CmmFloat f W64) = ImmDouble f
235 litToImm (CmmLabel l) = ImmCLbl l
236 litToImm (CmmLabelOff l off) = ImmIndex l off
237 litToImm (CmmLabelDiffOff l1 l2 off)
239 (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
241 litToImm (CmmBlock id) = ImmCLbl (infoTblLbl id)
243 -- -----------------------------------------------------------------------------
247 #if alpha_TARGET_ARCH
253 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
254 = AddrBaseIndex EABase EAIndex Displacement
257 data EABase = EABaseNone | EABaseReg Reg | EABaseRip
258 data EAIndex = EAIndexNone | EAIndex Reg Int
259 type Displacement = Imm
262 #if sparc_TARGET_ARCH
267 #if powerpc_TARGET_ARCH
272 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
273 addrModeRegs :: AddrMode -> [Reg]
274 addrModeRegs (AddrBaseIndex b i _) = b_regs ++ i_regs
276 b_regs = case b of { EABaseReg r -> [r]; _ -> [] }
277 i_regs = case i of { EAIndex r _ -> [r]; _ -> [] }
282 addrOffset :: AddrMode -> Int -> Maybe AddrMode
286 #if alpha_TARGET_ARCH
287 _ -> panic "MachMisc.addrOffset not defined for Alpha"
289 #if i386_TARGET_ARCH || x86_64_TARGET_ARCH
290 ImmAddr i off0 -> Just (ImmAddr i (off0 + off))
292 AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off)))
293 AddrBaseIndex r i (ImmInteger n)
294 -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off))))
296 AddrBaseIndex r i (ImmCLbl lbl)
297 -> Just (AddrBaseIndex r i (ImmIndex lbl off))
299 AddrBaseIndex r i (ImmIndex lbl ix)
300 -> Just (AddrBaseIndex r i (ImmIndex lbl (ix+off)))
302 _ -> Nothing -- in theory, shouldn't happen
304 #if sparc_TARGET_ARCH
305 AddrRegImm r (ImmInt n)
306 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt n2))
307 | otherwise -> Nothing
310 AddrRegImm r (ImmInteger n)
311 | fits13Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
312 | otherwise -> Nothing
313 where n2 = n + toInteger off
315 AddrRegReg r (RealReg 0)
316 | fits13Bits off -> Just (AddrRegImm r (ImmInt off))
317 | otherwise -> Nothing
321 #if powerpc_TARGET_ARCH
322 AddrRegImm r (ImmInt n)
323 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt n2))
324 | otherwise -> Nothing
327 AddrRegImm r (ImmInteger n)
328 | fits16Bits n2 -> Just (AddrRegImm r (ImmInt (fromInteger n2)))
329 | otherwise -> Nothing
330 where n2 = n + toInteger off
336 #if alpha_TARGET_ARCH
338 fits8Bits :: Integer -> Bool
339 fits8Bits i = i >= -256 && i < 256
343 #if sparc_TARGET_ARCH
345 {-# SPECIALIZE fits13Bits :: Int -> Bool, Integer -> Bool #-}
346 fits13Bits :: Integral a => a -> Bool
347 fits13Bits x = x >= -4096 && x < 4096
351 = error ("ERROR: SPARC native-code generator cannot handle large offset ("
352 ++show i++");\nprobably because of large constant data structures;" ++
353 "\nworkaround: use -fvia-C on this module.\n")
357 #if powerpc_TARGET_ARCH
358 fits16Bits :: Integral a => a -> Bool
359 fits16Bits x = x >= -32768 && x < 32768
361 makeImmediate :: Integral a => Width -> Bool -> a -> Maybe Imm
362 makeImmediate rep signed x = fmap ImmInt (toI16 rep signed)
364 narrow W32 False = fromIntegral (fromIntegral x :: Word32)
365 narrow W16 False = fromIntegral (fromIntegral x :: Word16)
366 narrow W8 False = fromIntegral (fromIntegral x :: Word8)
367 narrow W32 True = fromIntegral (fromIntegral x :: Int32)
368 narrow W16 True = fromIntegral (fromIntegral x :: Int16)
369 narrow W8 True = fromIntegral (fromIntegral x :: Int8)
371 narrowed = narrow rep signed
374 | narrowed >= -32768 && narrowed < 32768 = Just narrowed
375 | otherwise = Nothing
377 | narrowed >= 0 && narrowed < 65536 = Just narrowed
378 | otherwise = Nothing
379 toI16 _ _ = Just narrowed
383 -- @spRel@ gives us a stack relative addressing mode for volatile
384 -- temporaries and for excess call arguments. @fpRel@, where
385 -- applicable, is the same but for the frame pointer.
387 spRel :: Int -- desired stack offset in words, positive or negative
391 #if defined(i386_TARGET_ARCH)
392 = AddrBaseIndex (EABaseReg esp) EAIndexNone (ImmInt (n * wORD_SIZE))
393 #elif defined(x86_64_TARGET_ARCH)
394 = AddrBaseIndex (EABaseReg rsp) EAIndexNone (ImmInt (n * wORD_SIZE))
396 = AddrRegImm sp (ImmInt (n * wORD_SIZE))
399 #if sparc_TARGET_ARCH
400 fpRel :: Int -> AddrMode
401 -- Duznae work for offsets greater than 13 bits; we just hope for
404 = AddrRegImm fp (ImmInt (n * wORD_SIZE))
407 #if x86_64_TARGET_ARCH
408 ripRel imm = AddrBaseIndex EABaseRip EAIndexNone imm
411 -- -----------------------------------------------------------------------------
414 -- We map STG registers onto appropriate CmmExprs. Either they map
415 -- to real machine registers or stored as offsets from BaseReg. Given
416 -- a GlobalReg, get_GlobalReg_reg_or_addr produces either the real
417 -- register it is in, on this platform, or a CmmExpr denoting the
418 -- address in the register table holding it.
419 -- (See also get_GlobalReg_addr in CgUtils.)
421 get_GlobalReg_reg_or_addr :: GlobalReg -> Either Reg CmmExpr
422 get_GlobalReg_reg_or_addr mid
423 = case globalRegMaybe mid of
425 Nothing -> Right (get_GlobalReg_addr mid)
427 -- ---------------------------------------------------------------------------
430 -- RealRegs are machine regs which are available for allocation, in
431 -- the usual way. We know what class they are, because that's part of
432 -- the processor's architecture.
434 -- VirtualRegs are virtual registers. The register allocator will
435 -- eventually have to map them into RealRegs, or into spill slots.
436 -- VirtualRegs are allocated on the fly, usually to represent a single
437 -- value in the abstract assembly code (i.e. dynamic registers are
438 -- usually single assignment). With the new register allocator, the
439 -- single assignment restriction isn't necessary to get correct code,
440 -- although a better register allocation will result if single
441 -- assignment is used -- because the allocator maps a VirtualReg into
442 -- a single RealReg, even if the VirtualReg has multiple live ranges.
444 -- Virtual regs can be of either class, so that info is attached.
446 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
447 -- when supplied with the vreg for the lower-half of the quantity.
448 -- (NB. Not reversible).
449 getHiVRegFromLo (VirtualRegI u)
450 = VirtualRegHi (newTagUnique u 'H') -- makes a pseudo-unique with tag 'H'
451 getHiVRegFromLo other
452 = pprPanic "getHiVRegFromLo" (ppr other)
460 instance Uniquable RegClass where
461 getUnique RcInteger = mkUnique 'L' 0
462 getUnique RcFloat = mkUnique 'L' 1
463 getUnique RcDouble = mkUnique 'L' 2
468 = RealReg {-# UNPACK #-} !RegNo
469 | VirtualRegI {-# UNPACK #-} !Unique
470 | VirtualRegHi {-# UNPACK #-} !Unique -- High part of 2-word register
471 | VirtualRegF {-# UNPACK #-} !Unique
472 | VirtualRegD {-# UNPACK #-} !Unique
475 -- We like to have Uniques for Reg so that we can make UniqFM and UniqSets
476 -- in the register allocator.
477 instance Uniquable Reg where
478 getUnique (RealReg i) = mkUnique 'C' i
479 getUnique (VirtualRegI u) = u
480 getUnique (VirtualRegHi u) = u
481 getUnique (VirtualRegF u) = u
482 getUnique (VirtualRegD u) = u
484 unRealReg (RealReg i) = i
485 unRealReg vreg = pprPanic "unRealReg on VirtualReg" (ppr vreg)
487 mkVReg :: Unique -> Size -> Reg
489 | not (isFloatSize size) = VirtualRegI u
492 #if sparc_TARGET_ARCH
493 FF32 -> VirtualRegF u
495 FF32 -> VirtualRegD u
497 FF64 -> VirtualRegD u
498 _other -> panic "mkVReg"
500 isVirtualReg :: Reg -> Bool
501 isVirtualReg (RealReg _) = False
502 isVirtualReg (VirtualRegI _) = True
503 isVirtualReg (VirtualRegHi _) = True
504 isVirtualReg (VirtualRegF _) = True
505 isVirtualReg (VirtualRegD _) = True
507 isRealReg :: Reg -> Bool
508 isRealReg = not . isVirtualReg
510 renameVirtualReg :: Unique -> Reg -> Reg
513 RealReg _ -> error "renameVirtualReg: can't change unique on a real reg"
514 VirtualRegI _ -> VirtualRegI u
515 VirtualRegHi _ -> VirtualRegHi u
516 VirtualRegF _ -> VirtualRegF u
517 VirtualRegD _ -> VirtualRegD u
519 instance Show Reg where
520 show (RealReg i) = showReg i
521 show (VirtualRegI u) = "%vI_" ++ show u
522 show (VirtualRegHi u) = "%vHi_" ++ show u
523 show (VirtualRegF u) = "%vF_" ++ show u
524 show (VirtualRegD u) = "%vD_" ++ show u
526 instance Outputable RegClass where
527 ppr RcInteger = Outputable.text "I"
528 ppr RcFloat = Outputable.text "F"
529 ppr RcDouble = Outputable.text "D"
531 instance Outputable Reg where
532 ppr r = Outputable.text (show r)
537 -- trivColorable function for the graph coloring allocator
538 -- This gets hammered by scanGraph during register allocation,
539 -- so needs to be fairly efficient.
541 -- NOTE: This only works for arcitectures with just RcInteger and RcDouble
542 -- (which are disjoint) ie. x86, x86_64 and ppc
546 -- Doing a nice fold over the UniqSet makes trivColorable use
547 -- 32% of total compile time and 42% of total alloc when compiling SHA1.lhs from darcs.
549 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
550 trivColorable classN conflicts exclusions
553 acc :: Reg -> (Int, Int) -> (Int, Int)
556 RcInteger -> (cd+1, cf)
557 RcDouble -> (cd, cf+1)
558 _ -> panic "MachRegs.trivColorable: reg class not handled"
560 tmp = foldUniqSet acc (0, 0) conflicts
561 (countInt, countFloat) = foldUniqSet acc tmp exclusions
563 squeese = worst countInt classN RcInteger
564 + worst countFloat classN RcDouble
566 in squeese < allocatableRegsInClass classN
568 -- | Worst case displacement
569 -- node N of classN has n neighbors of class C.
571 -- We currently only have RcInteger and RcDouble, which don't conflict at all.
572 -- This is a bit boring compared to what's in RegArchX86.
574 worst :: Int -> RegClass -> RegClass -> Int
575 worst n classN classC
579 RcInteger -> min n (allocatableRegsInClass RcInteger)
584 RcDouble -> min n (allocatableRegsInClass RcDouble)
589 -- The number of allocatable regs is hard coded here so we can do a fast comparision
590 -- in trivColorable. It's ok if these numbers are _less_ than the actual number of
591 -- free regs, but they can't be more or the register conflict graph won't color.
593 -- There is an allocatableRegsInClass :: RegClass -> Int, but doing the unboxing
594 -- is too slow for us here.
596 -- Compare MachRegs.freeRegs and MachRegs.h to get these numbers.
599 #define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
600 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(6))
602 #elif x86_64_TARGET_ARCH
603 #define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
604 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(2))
606 #elif powerpc_TARGET_ARCH
607 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
608 #define ALLOCATABLE_REGS_DOUBLE (_ILIT(26))
611 #error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
614 {-# INLINE regClass #-}
615 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
616 trivColorable classN conflicts exclusions
617 = {-# SCC "trivColorable" #-}
619 {-# INLINE isSqueesed #-}
622 NodeUFM _ _ left right
623 -> case isSqueesed cI cF right of
626 False -> isSqueesed cI' cF' left
627 True -> (# True, cI', cF' #)
630 -> case regClass reg of
632 -> case cI +# _ILIT(1) of
633 cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
636 -> case cF +# _ILIT(1) of
637 cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE, cI, cF' #)
640 -> (# False, cI, cF #)
642 in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
643 (# False, cI', cF' #)
644 -> case isSqueesed cI' cF' exclusions of
645 (# s, _, _ #) -> not s
652 -- -----------------------------------------------------------------------------
653 -- Machine-specific register stuff
655 -- The Alpha has 64 registers of interest; 32 integer registers and 32 floating
656 -- point registers. The mapping of STG registers to alpha machine registers
657 -- is defined in StgRegs.h. We are, of course, prepared for any eventuality.
659 #if alpha_TARGET_ARCH
663 v0, f0, ra, pv, gp, sp, zeroh :: Reg
665 f0 = realReg (fReg 0)
666 ra = FixedReg ILIT(26)
668 gp = FixedReg ILIT(29)
669 sp = FixedReg ILIT(30)
670 zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method)
672 t9, t10, t11, t12 :: Reg
680 Intel x86 architecture:
681 - All registers except 7 (esp) are available for use.
682 - Only ebx, esi, edi and esp are available across a C call (they are callee-saves).
683 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
684 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
685 - Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable
686 fp registers, and 3-operand insns for them, and we translate this into
687 real stack-based x86 fp code after register allocation.
689 The fp registers are all Double registers; we don't have any RcFloat class
690 regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
696 fake0, fake1, fake2, fake3, fake4, fake5,
697 eax, ebx, ecx, edx, esp, ebp, esi, edi :: Reg
714 -- On x86, we might want to have an 8-bit RegClass, which would
715 -- contain just regs 1-4 (the others don't have 8-bit versions).
716 -- However, we can get away without this at the moment because the
717 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
718 regClass (RealReg i) = if i < 8 then RcInteger else RcDouble
719 regClass (VirtualRegI u) = RcInteger
720 regClass (VirtualRegHi u) = RcInteger
721 regClass (VirtualRegD u) = RcDouble
722 regClass (VirtualRegF u) = pprPanic "regClass(x86):VirtualRegF"
723 (ppr (VirtualRegF u))
726 = ["%eax", "%ebx", "%ecx", "%edx", "%esi", "%edi", "%ebp", "%esp",
727 "%fake0", "%fake1", "%fake2", "%fake3", "%fake4", "%fake5", "%fake6"]
729 showReg :: RegNo -> String
731 = if n >= 0 && n < 14
733 else "%unknown_x86_real_reg_" ++ show n
739 AMD x86_64 architecture:
740 - Registers 0-16 have 32-bit counterparts (eax, ebx etc.)
741 - Registers 0-7 have 16-bit counterparts (ax, bx etc.)
742 - Registers 0-3 have 8 bit counterparts (ah, bh etc.)
746 #if x86_64_TARGET_ARCH
748 rax, rbx, rcx, rdx, rsp, rbp, rsi, rdi,
749 r8, r9, r10, r11, r12, r13, r14, r15,
750 xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
751 xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 :: Reg
786 -- so we can re-use some x86 code:
796 xmm n = RealReg (16+n)
798 -- On x86, we might want to have an 8-bit RegClass, which would
799 -- contain just regs 1-4 (the others don't have 8-bit versions).
800 -- However, we can get away without this at the moment because the
801 -- only allocatable integer regs are also 8-bit compatible (1, 3, 4).
802 regClass (RealReg i) = if i < 16 then RcInteger else RcDouble
803 regClass (VirtualRegI u) = RcInteger
804 regClass (VirtualRegHi u) = RcInteger
805 regClass (VirtualRegD u) = RcDouble
806 regClass (VirtualRegF u) = pprPanic "regClass(x86_64):VirtualRegF"
807 (ppr (VirtualRegF u))
810 = ["%rax", "%rbx", "%rcx", "%rdx", "%rsi", "%rdi", "%rbp", "%rsp" ]
812 showReg :: RegNo -> String
814 | n >= 16 = "%xmm" ++ show (n-16)
815 | n >= 8 = "%r" ++ show n
816 | otherwise = regNames !! n
821 The SPARC has 64 registers of interest; 32 integer registers and 32
822 floating point registers. The mapping of STG registers to SPARC
823 machine registers is defined in StgRegs.h. We are, of course,
824 prepared for any eventuality.
826 The whole fp-register pairing thing on sparcs is a huge nuisance. See
827 fptools/ghc/includes/MachRegs.h for a description of what's going on
831 #if sparc_TARGET_ARCH
833 gReg,lReg,iReg,oReg,fReg :: Int -> RegNo
840 nCG_FirstFloatReg :: RegNo
841 nCG_FirstFloatReg = unRealReg NCG_FirstFloatReg
843 regClass (VirtualRegI u) = RcInteger
844 regClass (VirtualRegF u) = RcFloat
845 regClass (VirtualRegD u) = RcDouble
846 regClass (RealReg i) | i < 32 = RcInteger
847 | i < nCG_FirstFloatReg = RcDouble
848 | otherwise = RcFloat
850 showReg :: RegNo -> String
852 | n >= 0 && n < 8 = "%g" ++ show n
853 | n >= 8 && n < 16 = "%o" ++ show (n-8)
854 | n >= 16 && n < 24 = "%l" ++ show (n-16)
855 | n >= 24 && n < 32 = "%i" ++ show (n-24)
856 | n >= 32 && n < 64 = "%f" ++ show (n-32)
857 | otherwise = "%unknown_sparc_real_reg_" ++ show n
859 g0, g1, g2, fp, sp, o0, o1, f0, f1, f6, f8, f22, f26, f27 :: Reg
861 f6 = RealReg (fReg 6)
862 f8 = RealReg (fReg 8)
863 f22 = RealReg (fReg 22)
864 f26 = RealReg (fReg 26)
865 f27 = RealReg (fReg 27)
868 -- g0 is useful for codegen; is always zero, and writes to it vanish.
869 g0 = RealReg (gReg 0)
870 g1 = RealReg (gReg 1)
871 g2 = RealReg (gReg 2)
873 -- FP, SP, int and float return (from C) regs.
874 fp = RealReg (iReg 6)
875 sp = RealReg (oReg 6)
876 o0 = RealReg (oReg 0)
877 o1 = RealReg (oReg 1)
878 f0 = RealReg (fReg 0)
879 f1 = RealReg (fReg 1)
884 The PowerPC has 64 registers of interest; 32 integer registers and 32 floating
888 #if powerpc_TARGET_ARCH
892 regClass (VirtualRegI u) = RcInteger
893 regClass (VirtualRegHi u) = RcInteger
894 regClass (VirtualRegF u) = pprPanic "regClass(ppc):VirtualRegF"
895 (ppr (VirtualRegF u))
896 regClass (VirtualRegD u) = RcDouble
897 regClass (RealReg i) | i < 32 = RcInteger
898 | otherwise = RcDouble
900 showReg :: RegNo -> String
902 | n >= 0 && n <= 31 = "%r" ++ show n
903 | n >= 32 && n <= 63 = "%f" ++ show (n - 32)
904 | otherwise = "%unknown_powerpc_real_reg_" ++ show n
911 f1 = RealReg $ fReg 1
912 f20 = RealReg $ fReg 20
913 f21 = RealReg $ fReg 21
917 Redefine the literals used for machine-registers with non-numeric
918 names in the header files. Gag me with a spoon, eh?
921 #if alpha_TARGET_ARCH
972 #if x86_64_TARGET_ARCH
1007 #if sparc_TARGET_ARCH
1075 #if powerpc_TARGET_ARCH
1109 #ifdef darwin_TARGET_OS
1179 -- allMachRegs is the complete set of machine regs.
1180 allMachRegNos :: [RegNo]
1182 = IF_ARCH_alpha( [0..63],
1183 IF_ARCH_i386( [0..13],
1184 IF_ARCH_x86_64( [0..31],
1185 IF_ARCH_sparc( ([0..31]
1186 ++ [f0,f2 .. nCG_FirstFloatReg-1]
1187 ++ [nCG_FirstFloatReg .. f31]),
1188 IF_ARCH_powerpc([0..63],
1191 -- allocatableRegs is allMachRegNos with the fixed-use regs removed.
1192 -- i.e., these are the regs for which we are prepared to allow the
1193 -- register allocator to attempt to map VRegs to.
1194 allocatableRegs :: [RegNo]
1196 = let isFree i = isFastTrue (freeReg i)
1197 in filter isFree allMachRegNos
1200 -- | The number of regs in each class.
1201 -- We go via top level CAFs to ensure that we're not recomputing
1202 -- the length of these lists each time the fn is called.
1203 allocatableRegsInClass :: RegClass -> Int
1204 allocatableRegsInClass cls
1206 RcInteger -> allocatableRegsInteger
1207 RcDouble -> allocatableRegsDouble
1209 allocatableRegsInteger
1210 = length $ filter (\r -> regClass r == RcInteger)
1211 $ map RealReg allocatableRegs
1213 allocatableRegsDouble
1214 = length $ filter (\r -> regClass r == RcDouble)
1215 $ map RealReg allocatableRegs
1218 -- these are the regs which we cannot assume stay alive over a
1220 callClobberedRegs :: [Reg]
1223 #if alpha_TARGET_ARCH
1224 [0, 1, 2, 3, 4, 5, 6, 7, 8,
1225 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
1226 fReg 0, fReg 1, fReg 10, fReg 11, fReg 12, fReg 13, fReg 14, fReg 15,
1227 fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21, fReg 22, fReg 23,
1228 fReg 24, fReg 25, fReg 26, fReg 27, fReg 28, fReg 29, fReg 30]
1229 #endif /* alpha_TARGET_ARCH */
1230 #if i386_TARGET_ARCH
1231 -- caller-saves registers
1232 map RealReg [eax,ecx,edx,fake0,fake1,fake2,fake3,fake4,fake5]
1233 #endif /* i386_TARGET_ARCH */
1234 #if x86_64_TARGET_ARCH
1235 -- caller-saves registers
1236 map RealReg ([rax,rcx,rdx,rsi,rdi,r8,r9,r10,r11] ++ [16..31])
1237 -- all xmm regs are caller-saves
1238 #endif /* x86_64_TARGET_ARCH */
1239 #if sparc_TARGET_ARCH
1242 [oReg i | i <- [0..5]] ++
1243 [gReg i | i <- [1..7]] ++
1244 [fReg i | i <- [0..31]] )
1245 #endif /* sparc_TARGET_ARCH */
1246 #if powerpc_TARGET_ARCH
1247 #if darwin_TARGET_OS
1248 map RealReg (0:[2..12] ++ map fReg [0..13])
1249 #elif linux_TARGET_OS
1250 map RealReg (0:[2..13] ++ map fReg [0..13])
1252 #endif /* powerpc_TARGET_ARCH */
1255 -- argRegs is the set of regs which are read for an n-argument call to C.
1256 -- For archs which pass all args on the stack (x86), is empty.
1257 -- Sparc passes up to the first 6 args in regs.
1258 -- Dunno about Alpha.
1259 argRegs :: RegNo -> [Reg]
1261 #if i386_TARGET_ARCH
1262 argRegs _ = panic "MachRegs.argRegs(x86): should not be used!"
1265 #if x86_64_TARGET_ARCH
1266 argRegs _ = panic "MachRegs.argRegs(x86_64): should not be used!"
1269 #if alpha_TARGET_ARCH
1271 argRegs 1 = freeMappedRegs [16, fReg 16]
1272 argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17]
1273 argRegs 3 = freeMappedRegs [16, 17, 18, fReg 16, fReg 17, fReg 18]
1274 argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19]
1275 argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20]
1276 argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21]
1277 argRegs _ = panic "MachRegs.argRegs(alpha): don't know about >6 arguments!"
1278 #endif /* alpha_TARGET_ARCH */
1280 #if sparc_TARGET_ARCH
1282 argRegs 1 = map (RealReg . oReg) [0]
1283 argRegs 2 = map (RealReg . oReg) [0,1]
1284 argRegs 3 = map (RealReg . oReg) [0,1,2]
1285 argRegs 4 = map (RealReg . oReg) [0,1,2,3]
1286 argRegs 5 = map (RealReg . oReg) [0,1,2,3,4]
1287 argRegs 6 = map (RealReg . oReg) [0,1,2,3,4,5]
1288 argRegs _ = panic "MachRegs.argRegs(sparc): don't know about >6 arguments!"
1289 #endif /* sparc_TARGET_ARCH */
1291 #if powerpc_TARGET_ARCH
1293 argRegs 1 = map RealReg [3]
1294 argRegs 2 = map RealReg [3,4]
1295 argRegs 3 = map RealReg [3..5]
1296 argRegs 4 = map RealReg [3..6]
1297 argRegs 5 = map RealReg [3..7]
1298 argRegs 6 = map RealReg [3..8]
1299 argRegs 7 = map RealReg [3..9]
1300 argRegs 8 = map RealReg [3..10]
1301 argRegs _ = panic "MachRegs.argRegs(powerpc): don't know about >8 arguments!"
1302 #endif /* powerpc_TARGET_ARCH */
1305 -- all of the arg regs ??
1306 #if alpha_TARGET_ARCH
1307 allArgRegs :: [(Reg, Reg)]
1308 allArgRegs = [(realReg i, realReg (fReg i)) | i <- [16..21]]
1309 #endif /* alpha_TARGET_ARCH */
1311 #if sparc_TARGET_ARCH
1313 allArgRegs = map RealReg [oReg i | i <- [0..5]]
1314 #endif /* sparc_TARGET_ARCH */
1316 #if i386_TARGET_ARCH
1318 allArgRegs = panic "MachRegs.allArgRegs(x86): should not be used!"
1321 #if x86_64_TARGET_ARCH
1323 allArgRegs = map RealReg [rdi,rsi,rdx,rcx,r8,r9]
1324 allFPArgRegs :: [Reg]
1325 allFPArgRegs = map RealReg [xmm0 .. xmm7]
1328 #if powerpc_TARGET_ARCH
1330 allArgRegs = map RealReg [3..10]
1331 allFPArgRegs :: [Reg]
1332 #if darwin_TARGET_OS
1333 allFPArgRegs = map (RealReg . fReg) [1..13]
1334 #elif linux_TARGET_OS
1335 allFPArgRegs = map (RealReg . fReg) [1..8]
1337 #endif /* powerpc_TARGET_ARCH */
1341 freeReg :: RegNo -> FastBool
1343 #if alpha_TARGET_ARCH
1344 freeReg 26 = fastBool False -- return address (ra)
1345 freeReg 28 = fastBool False -- reserved for the assembler (at)
1346 freeReg 29 = fastBool False -- global pointer (gp)
1347 freeReg 30 = fastBool False -- stack pointer (sp)
1348 freeReg 31 = fastBool False -- always zero (zeroh)
1349 freeReg 63 = fastBool False -- always zero (f31)
1352 #if i386_TARGET_ARCH
1353 freeReg esp = fastBool False -- %esp is the C stack pointer
1356 #if x86_64_TARGET_ARCH
1357 freeReg rsp = fastBool False -- %rsp is the C stack pointer
1360 #if sparc_TARGET_ARCH
1361 freeReg g0 = fastBool False -- %g0 is always 0.
1362 freeReg g5 = fastBool False -- %g5 is reserved (ABI).
1363 freeReg g6 = fastBool False -- %g6 is reserved (ABI).
1364 freeReg g7 = fastBool False -- %g7 is reserved (ABI).
1365 freeReg i6 = fastBool False -- %i6 is our frame pointer.
1366 freeReg i7 = fastBool False -- %i7 tends to have ret-addr-ish things
1367 freeReg o6 = fastBool False -- %o6 is our stack pointer.
1368 freeReg o7 = fastBool False -- %o7 holds ret addrs (???)
1369 freeReg f0 = fastBool False -- %f0/%f1 are the C fp return registers.
1370 freeReg f1 = fastBool False
1373 #if powerpc_TARGET_ARCH
1374 freeReg 0 = fastBool False -- Hack: r0 can't be used in all insns, but it's actually free
1375 freeReg 1 = fastBool False -- The Stack Pointer
1376 #if !darwin_TARGET_OS
1377 -- most non-darwin powerpc OSes use r2 as a TOC pointer or something like that
1378 freeReg 2 = fastBool False
1383 freeReg REG_Base = fastBool False
1386 freeReg REG_R1 = fastBool False
1389 freeReg REG_R2 = fastBool False
1392 freeReg REG_R3 = fastBool False
1395 freeReg REG_R4 = fastBool False
1398 freeReg REG_R5 = fastBool False
1401 freeReg REG_R6 = fastBool False
1404 freeReg REG_R7 = fastBool False
1407 freeReg REG_R8 = fastBool False
1410 freeReg REG_F1 = fastBool False
1413 freeReg REG_F2 = fastBool False
1416 freeReg REG_F3 = fastBool False
1419 freeReg REG_F4 = fastBool False
1422 freeReg REG_D1 = fastBool False
1425 freeReg REG_D2 = fastBool False
1428 freeReg REG_Sp = fastBool False
1431 freeReg REG_Su = fastBool False
1434 freeReg REG_SpLim = fastBool False
1437 freeReg REG_Hp = fastBool False
1440 freeReg REG_HpLim = fastBool False
1442 freeReg n = fastBool True
1445 -- | Returns 'Nothing' if this global register is not stored
1446 -- in a real machine register, otherwise returns @'Just' reg@, where
1447 -- reg is the machine register it is stored in.
1449 globalRegMaybe :: GlobalReg -> Maybe Reg
1452 globalRegMaybe BaseReg = Just (RealReg REG_Base)
1455 globalRegMaybe (VanillaReg 1 _) = Just (RealReg REG_R1)
1458 globalRegMaybe (VanillaReg 2 _) = Just (RealReg REG_R2)
1461 globalRegMaybe (VanillaReg 3 _) = Just (RealReg REG_R3)
1464 globalRegMaybe (VanillaReg 4 _) = Just (RealReg REG_R4)
1467 globalRegMaybe (VanillaReg 5 _) = Just (RealReg REG_R5)
1470 globalRegMaybe (VanillaReg 6 _) = Just (RealReg REG_R6)
1473 globalRegMaybe (VanillaReg 7 _) = Just (RealReg REG_R7)
1476 globalRegMaybe (VanillaReg 8 _) = Just (RealReg REG_R8)
1479 globalRegMaybe (VanillaReg 9 _) = Just (RealReg REG_R9)
1482 globalRegMaybe (VanillaReg 10 _) = Just (RealReg REG_R10)
1485 globalRegMaybe (FloatReg 1) = Just (RealReg REG_F1)
1488 globalRegMaybe (FloatReg 2) = Just (RealReg REG_F2)
1491 globalRegMaybe (FloatReg 3) = Just (RealReg REG_F3)
1494 globalRegMaybe (FloatReg 4) = Just (RealReg REG_F4)
1497 globalRegMaybe (DoubleReg 1) = Just (RealReg REG_D1)
1500 globalRegMaybe (DoubleReg 2) = Just (RealReg REG_D2)
1503 globalRegMaybe Sp = Just (RealReg REG_Sp)
1506 globalRegMaybe (LongReg 1) = Just (RealReg REG_Lng1)
1509 globalRegMaybe (LongReg 2) = Just (RealReg REG_Lng2)
1512 globalRegMaybe SpLim = Just (RealReg REG_SpLim)
1515 globalRegMaybe Hp = Just (RealReg REG_Hp)
1518 globalRegMaybe HpLim = Just (RealReg REG_HpLim)
1520 #ifdef REG_CurrentTSO
1521 globalRegMaybe CurrentTSO = Just (RealReg REG_CurrentTSO)
1523 #ifdef REG_CurrentNursery
1524 globalRegMaybe CurrentNursery = Just (RealReg REG_CurrentNursery)
1526 globalRegMaybe _ = Nothing