Split Reg into vreg/hreg and add register pairs

[ghc-hetmet.git] / compiler / nativeGen / RegAlloc / Linear / Base.hs

diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index 95c9965..2626232 100644 (file)
--- a/compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs
@@ -3,7 +3,9 @@
 
 module RegAlloc.Linear.Base (
        BlockAssignment,
+
        Loc(..),
+       regsOfLoc,
 
        -- for stats
        SpillReason(..),
@@ -18,9 +20,8 @@ where
 
 import RegAlloc.Linear.FreeRegs
 import RegAlloc.Linear.StackMap
-
-import RegLiveness
-import MachRegs
+import RegAlloc.Liveness
+import Reg
 
 import Outputable
 import Unique
@@ -50,14 +51,14 @@ type BlockAssignment
 --
 data Loc 
        -- | vreg is in a register
-       = InReg   {-# UNPACK #-} !RegNo
+       = InReg   {-# UNPACK #-}  !RealReg
 
        -- | vreg is held in a stack slot
-       | InMem   {-# UNPACK #-} !StackSlot
+       | InMem   {-# UNPACK #-}  !StackSlot
 
 
        -- | vreg is held in both a register and a stack slot
-       | InBoth  {-# UNPACK #-}  !RegNo
+       | InBoth  {-# UNPACK #-}  !RealReg
                   {-# UNPACK #-} !StackSlot
        deriving (Eq, Show, Ord)
 
@@ -65,6 +66,13 @@ instance Outputable Loc where
        ppr l = text (show l)
 
 
+-- | Get the reg numbers stored in this Loc.
+regsOfLoc :: Loc -> [RealReg]
+regsOfLoc (InReg r)    = [r]
+regsOfLoc (InBoth r _) = [r]
+regsOfLoc (InMem _)    = []
+
+
 -- | Reasons why instructions might be inserted by the spiller.
 --     Used when generating stats for -ddrop-asm-stats.
 --
@@ -96,9 +104,10 @@ data RegAllocStats
 data RA_State 
        = RA_State 
 
+       { 
        -- | the current mapping from basic blocks to 
        --      the register assignments at the beginning of that block.
-       { ra_blockassig :: BlockAssignment
+         ra_blockassig :: BlockAssignment
        
        -- | free machine registers
        , ra_freeregs   :: {-#UNPACK#-}!FreeRegs