Split Reg into vreg/hreg and add register pairs

[ghc-hetmet.git] / compiler / nativeGen / RegAlloc / Linear / Base.hs

diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index ebd3107..2626232 100644 (file)
--- a/compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs
@@ -20,9 +20,8 @@ where
 
 import RegAlloc.Linear.FreeRegs
 import RegAlloc.Linear.StackMap
-
-import RegLiveness
-import Regs
+import RegAlloc.Liveness
+import Reg
 
 import Outputable
 import Unique
@@ -52,14 +51,14 @@ type BlockAssignment
 --
 data Loc 
        -- | vreg is in a register
-       = InReg   {-# UNPACK #-} !RegNo
+       = InReg   {-# UNPACK #-}  !RealReg
 
        -- | vreg is held in a stack slot
-       | InMem   {-# UNPACK #-} !StackSlot
+       | InMem   {-# UNPACK #-}  !StackSlot
 
 
        -- | vreg is held in both a register and a stack slot
-       | InBoth  {-# UNPACK #-}  !RegNo
+       | InBoth  {-# UNPACK #-}  !RealReg
                   {-# UNPACK #-} !StackSlot
        deriving (Eq, Show, Ord)
 
@@ -68,7 +67,7 @@ instance Outputable Loc where
 
 
 -- | Get the reg numbers stored in this Loc.
-regsOfLoc :: Loc -> [RegNo]
+regsOfLoc :: Loc -> [RealReg]
 regsOfLoc (InReg r)    = [r]
 regsOfLoc (InBoth r _) = [r]
 regsOfLoc (InMem _)    = []