import Reg
import BlockId
-import Cmm hiding (RegSet)
+import OldCmm hiding (RegSet)
import Digraph
import Outputable
import Unique
-> BlockId -- ^ id of the current block
-> instr -- ^ branch instr on the end of the source block.
- -> RegM ([NatBasicBlock instr] -- fresh blocks of fixup code.
+ -> RegM FreeRegs ([NatBasicBlock instr] -- fresh blocks of fixup code.
, instr) -- the original branch instruction, but maybe patched to jump
-- to a fixup block first.
-> [BlockId] -- ^ branch destinations still to consider.
- -> RegM ( [NatBasicBlock instr]
+ -> RegM FreeRegs ( [NatBasicBlock instr]
, instr)
-- no more targets to consider. all done.
-- adjust the current assignment to remove any vregs that are not live
-- on entry to the destination block.
- let Just live_set = lookupBlockEnv block_live dest
+ let Just live_set = mapLookup dest block_live
let still_live uniq _ = uniq `elemUniqSet_Directly` live_set
let adjusted_assig = filterUFM_Directly still_live assig
, not (elemUniqSet_Directly reg live_set)
, r <- regsOfLoc loc ]
- case lookupBlockEnv block_assig dest of
+ case mapLookup dest block_assig of
Nothing
-> joinToTargets_first
block_live new_blocks block_id instr dest dests
let freeregs' = foldr releaseReg freeregs to_free
-- remember the current assignment on entry to this block.
- setBlockAssigR (extendBlockEnv block_assig dest
- (freeregs', src_assig))
+ setBlockAssigR (mapInsert dest (freeregs', src_assig) block_assig)
joinToTargets' block_live new_blocks block_id instr dests
-- A the end of the current block we will jump to the fixup one,
-- then that will jump to our original destination.
fixup_block_id <- getUniqueR
- let block = BasicBlock (BlockId fixup_block_id)
+ let block = BasicBlock (mkBlockId fixup_block_id)
$ fixUpInstrs ++ mkJumpInstr dest
{- pprTrace
-- fixup block instead.
_ -> let instr' = patchJumpInstr instr
(\bid -> if bid == dest
- then BlockId fixup_block_id
- else dest)
+ then mkBlockId fixup_block_id
+ else bid) -- no change!
in joinToTargets' block_live (block : new_blocks) block_id instr' dests
--
handleComponent
:: Instruction instr
- => Int -> instr -> SCC (Unique, Loc, [Loc]) -> RegM [instr]
+ => Int -> instr -> SCC (Unique, Loc, [Loc]) -> RegM FreeRegs [instr]
-- If the graph is acyclic then we won't get the swapping problem below.
-- In this case we can just do the moves directly, and avoid having to
-- require a fixup.
--
handleComponent delta instr
- (CyclicSCC ( (vreg, InReg sreg, [InReg dreg]) : rest))
+ (CyclicSCC ( (vreg, InReg sreg, (InReg dreg: _)) : rest))
+ -- dest list may have more than one element, if the reg is also InMem.
= do
-- spill the source into its slot
(instrSpill, slot)
-> Unique -- ^ unique of the vreg that we're moving.
-> Loc -- ^ source location.
-> Loc -- ^ destination location.
- -> RegM instr -- ^ move instruction.
+ -> RegM FreeRegs instr -- ^ move instruction.
makeMove _ vreg (InReg src) (InReg dst)
= do recordSpill (SpillJoinRR vreg)