update Sparc store/load barrier (#3019), and fix comments

[ghc-hetmet.git] / includes / SMP.h

diff --git a/includes/SMP.h b/includes/SMP.h
index c851054..ac98feb 100644 (file)
--- a/includes/SMP.h
+++ b/includes/SMP.h
@@ -179,7 +179,7 @@ write_barrier(void) {
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
+    /* Sparc in TSO mode does not require store/store barriers. */
     __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;
@@ -195,10 +195,9 @@ store_load_barrier(void) {
 #elif x86_64_HOST_ARCH
     __asm__ __volatile__ ("lock; addq $0,0(%%rsp)" : : : "memory");
 #elif powerpc_HOST_ARCH
-    __asm__ __volatile__ ("msync" : : : "memory");
+    __asm__ __volatile__ ("sync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
-    __asm__ __volatile__ ("membar" : : : "memory");
+    __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
 #elif !defined(WITHSMP)
     return;
 #else
@@ -215,7 +214,7 @@ load_load_barrier(void) {
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
+    /* Sparc in TSO mode does not require load/load barriers. */
     __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;