X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=blobdiff_plain;f=compiler%2FnativeGen%2FMachInstrs.hs;h=0c5dbdd1ed807e0d359c78c98fd513fb8ee747be;hp=a9b04db3e57872dc4d01b816e19141fb39a2ee2e;hb=0168c633a9d209e978528f059193d19cdb5e6740;hpb=e4c8d2b11b4be71885532cb14434511b6c47866c

diff --git a/compiler/nativeGen/MachInstrs.hs b/compiler/nativeGen/MachInstrs.hs
index a9b04db..0c5dbdd 100644
--- a/compiler/nativeGen/MachInstrs.hs
+++ b/compiler/nativeGen/MachInstrs.hs
@@ -52,8 +52,8 @@ import GHC.Exts
 -- Our flavours of the Cmm types
 
 -- Type synonyms for Cmm populated with native code
-type NatCmm        = GenCmm CmmStatic Instr
-type NatCmmTop     = GenCmmTop CmmStatic Instr
+type NatCmm        = GenCmm CmmStatic [CmmStatic] Instr
+type NatCmmTop     = GenCmmTop CmmStatic [CmmStatic] Instr
 type NatBasicBlock = GenBasicBlock Instr
 
 -- -----------------------------------------------------------------------------
@@ -226,6 +226,9 @@ data Instr
   | DELTA   Int                 -- specify current stack offset for
                                 -- benefit of subsequent passes
 
+  | SPILL   Reg Int		-- ^ spill this reg to a stack slot
+  | RELOAD  Int Reg		-- ^ reload this reg from a stack slot
+
 -- -----------------------------------------------------------------------------
 -- Alpha instructions
 
@@ -488,8 +491,8 @@ bit or 64 bit precision.
 
 	| CVTSS2SD	Reg Reg		-- F32 to F64
 	| CVTSD2SS	Reg Reg		-- F64 to F32
-	| CVTSS2SI	Operand Reg	-- F32 to I32/I64 (with rounding)
-	| CVTSD2SI	Operand	Reg	-- F64 to I32/I64 (with rounding)
+	| CVTTSS2SIQ	Operand Reg	-- F32 to I32/I64 (with truncation)
+	| CVTTSD2SIQ	Operand	Reg	-- F64 to I32/I64 (with truncation)
 	| CVTSI2SS	Operand Reg	-- I32/I64 to F32
 	| CVTSI2SD	Operand Reg	-- I32/I64 to F64
 
@@ -520,6 +523,7 @@ bit or 64 bit precision.
 -- Jumping around.
 	| JMP	      Operand
 	| JXX	      Cond BlockId  -- includes unconditional branches
+	| JXX_GBL     Cond Imm      -- non-local version of JXX
 	| JMP_TBL     Operand [BlockId]  -- table jump
 	| CALL	      (Either Imm Reg) [Reg]