X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAlloc%2FLinear%2FBase.hs;fp=compiler%2FnativeGen%2FRegAlloc%2FLinear%2FBase.hs;h=432acdf314111f7e741d54defce020049cd96459;hp=fc8d4edef6f17cb0cfd9a9f9332e6248cc68cee6;hb=3c2a7f3515ca15cdebb6242967f89e633cb59494;hpb=59244201b672b9d6f728edcf7e2e02a61fbe278f

diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index fc8d4ed..432acdf 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs
@@ -18,7 +18,6 @@ module RegAlloc.Linear.Base (
 
 where
 
-import RegAlloc.Linear.FreeRegs
 import RegAlloc.Linear.StackMap
 import RegAlloc.Liveness
 import Reg
@@ -34,8 +33,8 @@ import UniqSupply
 --      target a particular label. We have to insert fixup code to make
 --      the register assignments from the different sources match up.
 --
-type BlockAssignment
-        = BlockMap (FreeRegs, RegMap Loc)
+type BlockAssignment freeRegs
+        = BlockMap (freeRegs, RegMap Loc)
 
 
 -- | Where a vreg is currently stored
@@ -107,7 +106,7 @@ data RA_State freeRegs
         {
         -- | the current mapping from basic blocks to
         --      the register assignments at the beginning of that block.
-          ra_blockassig :: BlockAssignment
+          ra_blockassig :: BlockAssignment freeRegs
 
         -- | free machine registers
         , ra_freeregs   :: !freeRegs