X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAllocInfo.hs;h=376ea489b5b2374b4504b56aa121aea61a009a2d;hp=fefa31487e7d5428716e1660437370b96ab831a8;hb=7fc749a43b4b6b85d234fa95d4928648259584f4;hpb=22bbcd1dcd94851b8f9409310cf95f3b9332850c

diff --git a/compiler/nativeGen/RegAllocInfo.hs b/compiler/nativeGen/RegAllocInfo.hs
index fefa314..376ea48 100644
--- a/compiler/nativeGen/RegAllocInfo.hs
+++ b/compiler/nativeGen/RegAllocInfo.hs
@@ -6,6 +6,13 @@
 --
 -----------------------------------------------------------------------------
 
+{-# OPTIONS -w #-}
+-- The above warning supression flag is a temporary kludge.
+-- While working on this module you are encouraged to remove it and fix
+-- any warnings in the module. See
+--     http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
+-- for details
+
 #include "nativeGen/NCG.h"
 
 module RegAllocInfo (
@@ -69,6 +76,8 @@ interesting (RealReg i)       = isFastTrue (freeReg i)
 
 #if alpha_TARGET_ARCH
 regUsage instr = case instr of
+    SPILL  reg slot	-> usage ([reg], [])
+    RELOAD slot reg	-> usage ([], [reg])
     LD B reg addr	-> usage (regAddr addr, [reg, t9])
     LD Bu reg addr	-> usage (regAddr addr, [reg, t9])
 --  LD W reg addr	-> usage (regAddr addr, [reg, t9]) : UNUSED
@@ -214,8 +223,8 @@ regUsage instr = case instr of
 #if x86_64_TARGET_ARCH
     CVTSS2SD src dst	-> mkRU [src] [dst]
     CVTSD2SS src dst	-> mkRU [src] [dst]
-    CVTSS2SI src dst	-> mkRU (use_R src) [dst]
-    CVTSD2SI src dst	-> mkRU (use_R src) [dst]
+    CVTTSS2SIQ src dst	-> mkRU (use_R src) [dst]
+    CVTTSD2SIQ src dst	-> mkRU (use_R src) [dst]
     CVTSI2SS src dst	-> mkRU (use_R src) [dst]
     CVTSI2SD src dst	-> mkRU (use_R src) [dst]
     FDIV sz src dst     -> usageRM src dst
@@ -226,6 +235,8 @@ regUsage instr = case instr of
 
     COMMENT _		-> noUsage
     DELTA   _           -> noUsage
+    SPILL   reg slot	-> mkRU [reg] []
+    RELOAD  slot reg	-> mkRU []    [reg]
 
     _other		-> panic "regUsage: unrecognised instr"
 
@@ -275,6 +286,9 @@ regUsage instr = case instr of
 #if sparc_TARGET_ARCH
 
 regUsage instr = case instr of
+    SPILL reg slot	-> usage ([reg], [])
+    RELOAD slot reg	-> usage ([], [reg])
+
     LD    sz addr reg  	-> usage (regAddr addr, [reg])
     ST    sz reg addr  	-> usage (reg : regAddr addr, [])
     ADD   x cc r1 ar r2	-> usage (r1 : regRI ar, [r2])
@@ -327,6 +341,9 @@ regUsage instr = case instr of
 #if powerpc_TARGET_ARCH
 
 regUsage instr = case instr of
+    SPILL  reg slot	-> usage ([reg], [])
+    RELOAD slot reg	-> usage ([], [reg])
+
     LD    sz reg addr  	-> usage (regAddr addr, [reg])
     LA    sz reg addr  	-> usage (regAddr addr, [reg])
     ST    sz reg addr  	-> usage (reg : regAddr addr, [])
@@ -471,6 +488,8 @@ patchRegs :: Instr -> (Reg -> Reg) -> Instr
 #if alpha_TARGET_ARCH
 
 patchRegs instr env = case instr of
+    SPILL  reg slot	-> SPILL (env reg) slot
+    RELOAD slot reg	-> RELOAD slot (env reg)
     LD sz reg addr -> LD sz (env reg) (fixAddr addr)
     LDA reg addr -> LDA (env reg) (fixAddr addr)
     LDAH reg addr -> LDAH (env reg) (fixAddr addr)
@@ -588,8 +607,8 @@ patchRegs instr env = case instr of
 #if x86_64_TARGET_ARCH
     CVTSS2SD src dst	-> CVTSS2SD (env src) (env dst)
     CVTSD2SS src dst	-> CVTSD2SS (env src) (env dst)
-    CVTSS2SI src dst	-> CVTSS2SI (patchOp src) (env dst)
-    CVTSD2SI src dst	-> CVTSD2SI (patchOp src) (env dst)
+    CVTTSS2SIQ src dst	-> CVTTSS2SIQ (patchOp src) (env dst)
+    CVTTSD2SIQ src dst	-> CVTTSD2SIQ (patchOp src) (env dst)
     CVTSI2SS src dst	-> CVTSI2SS (patchOp src) (env dst)
     CVTSI2SD src dst	-> CVTSI2SD (patchOp src) (env dst)
     FDIV sz src dst	-> FDIV sz (patchOp src) (patchOp dst)
@@ -604,6 +623,9 @@ patchRegs instr env = case instr of
     NOP			-> instr
     COMMENT _		-> instr
     DELTA _ 		-> instr
+    SPILL  reg slot	-> SPILL (env reg) slot
+    RELOAD slot reg	-> RELOAD slot (env reg)
+
     JXX _ _		-> instr
     JXX_GBL _ _		-> instr
     CLTD _		-> instr
@@ -634,6 +656,8 @@ patchRegs instr env = case instr of
 #if sparc_TARGET_ARCH
 
 patchRegs instr env = case instr of
+    SPILL reg slot	-> SPILL (env reg) slot
+    RELOAD slot reg	-> RELOAD slot (env reg)
     LD    sz addr reg   -> LD sz (fixAddr addr) (env reg)
     ST    sz reg addr   -> ST sz (env reg) (fixAddr addr)
     ADD   x cc r1 ar r2 -> ADD x cc (env r1) (fixRI ar) (env r2)
@@ -677,6 +701,9 @@ patchRegs instr env = case instr of
 #if powerpc_TARGET_ARCH
 
 patchRegs instr env = case instr of
+    SPILL reg slot	-> SPILL (env reg) slot
+    RELOAD slot reg	-> RELOAD slot (env reg)
+
     LD    sz reg addr   -> LD sz (env reg) (fixAddr addr)
     LA    sz reg addr   -> LA sz (env reg) (fixAddr addr)
     ST    sz reg addr   -> ST sz (env reg) (fixAddr addr)
@@ -755,14 +782,12 @@ isRegRegMove _ = Nothing
 -- Generating spill instructions
 
 mkSpillInstr
-   :: Reg		-- register to spill (should be a real)
+   :: Reg		-- register to spill
    -> Int		-- current stack delta
    -> Int		-- spill slot to use
    -> Instr
 mkSpillInstr reg delta slot
-  = ASSERT(isRealReg reg)
-    let	
-        off     = spillSlotToOffset slot
+  = let	off     = spillSlotToOffset slot
     in
 #ifdef alpha_TARGET_ARCH
     {-Alpha: spill below the stack pointer (?)-}
@@ -800,14 +825,12 @@ mkSpillInstr reg delta slot
 
 
 mkLoadInstr
-   :: Reg		-- register to load (should be a real)
+   :: Reg		-- register to load
    -> Int		-- current stack delta
    -> Int		-- spill slot to use
    -> Instr
 mkLoadInstr reg delta slot
-  = ASSERT(isRealReg reg)
-    let
-        off     = spillSlotToOffset slot
+  = let off     = spillSlotToOffset slot
     in
 #if alpha_TARGET_ARCH
 	 LD  sz dyn (spRel (- (off `div` 8)))
@@ -891,4 +914,5 @@ spillSlotToOffset slot
    = 64 + spillSlotSize * slot
    | otherwise
    = pprPanic "spillSlotToOffset:" 
-              (text "invalid spill location: " <> int slot)
+              (   text "invalid spill location: " <> int slot
+	      $$  text "maxSpillSlots:          " <> int maxSpillSlots)