X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=blobdiff_plain;f=compiler%2FnativeGen%2FSPARC%2FInstr.hs;h=87b6abc317282508b36a94e22f646fb35a49d127;hp=30067825fab78f4453dc6fc346372b16c5717e36;hb=703ca1542c8e0983cc9d8eebce6e9f3dd3fd71e2;hpb=0bff9925654d75ef0fd8fb5d48b700337ebd8f47

diff --git a/compiler/nativeGen/SPARC/Instr.hs b/compiler/nativeGen/SPARC/Instr.hs
index 3006782..87b6abc 100644
--- a/compiler/nativeGen/SPARC/Instr.hs
+++ b/compiler/nativeGen/SPARC/Instr.hs
@@ -29,7 +29,9 @@ import SPARC.Imm
 import SPARC.AddrMode
 import SPARC.Cond
 import SPARC.Regs
+import SPARC.RegPlate
 import SPARC.Base
+import TargetReg
 import Instruction
 import RegClass
 import Reg
@@ -39,8 +41,7 @@ import BlockId
 import Cmm
 import FastString
 import FastBool
-
-import GHC.Exts
+import Outputable
 
 
 -- | Register or immediate
@@ -52,11 +53,11 @@ data RI
 --  	- a literal zero
 --	- register %g0, which is always zero.
 --
-riZero :: RI -> Bool
-riZero (RIImm (ImmInt 0))	    = True
-riZero (RIImm (ImmInteger 0))	    = True
-riZero (RIReg (RealReg 0))          = True
-riZero _			    = False
+riZero :: RI -> Bool	
+riZero (RIImm (ImmInt 0))			= True
+riZero (RIImm (ImmInteger 0))			= True
+riZero (RIReg (RegReal (RealRegSingle 0)))	= True
+riZero _					= False
 
 
 -- | Calculate the effective address which would be used by the
@@ -270,11 +271,9 @@ sparc_regUsageOfInstr instr
 interesting :: Reg -> Bool
 interesting reg
  = case reg of
- 	VirtualRegI  _	-> True
-	VirtualRegHi _	-> True
-	VirtualRegF  _	-> True
-	VirtualRegD  _	-> True
-	RealReg i	-> isFastTrue (freeReg i)
+	RegVirtual _			-> True
+	RegReal (RealRegSingle r1)	-> isFastTrue (freeReg r1)
+	RegReal (RealRegPair r1 _)	-> isFastTrue (freeReg r1)
 
 
 
@@ -370,7 +369,7 @@ sparc_mkSpillInstr
 sparc_mkSpillInstr reg _ slot
  = let	off     = spillSlotToOffset slot
         off_w	= 1 + (off `div` 4)
-        sz 	= case regClass reg of
+        sz 	= case targetClassOfReg reg of
 			RcInteger -> II32
 			RcFloat   -> FF32
 			RcDouble  -> FF64
@@ -380,7 +379,7 @@ sparc_mkSpillInstr reg _ slot
 
 -- | Make a spill reload instruction.
 sparc_mkLoadInstr
-	:: Reg		-- ^ register to load
+	:: Reg		-- ^ register to load into
 	-> Int		-- ^ current stack delta
 	-> Int		-- ^ spill slot to use
 	-> Instr
@@ -388,7 +387,7 @@ sparc_mkLoadInstr
 sparc_mkLoadInstr reg _ slot
   = let off     = spillSlotToOffset slot
 	off_w	= 1 + (off `div` 4)
-        sz	= case regClass reg of
+        sz	= case targetClassOfReg reg of
 			RcInteger -> II32
 			RcFloat   -> FF32
 			RcDouble  -> FF64
@@ -432,10 +431,16 @@ sparc_mkRegRegMoveInstr
 	-> Instr
 
 sparc_mkRegRegMoveInstr src dst
- = case regClass src of
-	RcInteger -> ADD  False False src (RIReg g0) dst
-	RcDouble  -> FMOV FF64 src dst
-	RcFloat   -> FMOV FF32 src dst
+	| srcClass	<- targetClassOfReg src
+	, dstClass	<- targetClassOfReg dst
+	, srcClass == dstClass
+	= case srcClass of
+		RcInteger -> ADD  False False src (RIReg g0) dst
+		RcDouble  -> FMOV FF64 src dst
+		RcFloat   -> FMOV FF32 src dst
+	
+	| otherwise
+	= panic "SPARC.Instr.mkRegRegMoveInstr: classes of src and dest not the same"
 
 
 -- | Check whether an instruction represents a reg-reg move.