X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=blobdiff_plain;f=compiler%2FnativeGen%2FSPARC%2FRegs.hs;h=cd19138aa4179e18805092af5b8030d73cff8db1;hp=8ad400f813e079abfea53dab8eeb5c5c58d2ba82;hb=335b9f366ac440259318777c4c07e4fa42fbbec6;hpb=d9f7177402769968e8f42b49c1941661e18c5773

diff --git a/compiler/nativeGen/SPARC/Regs.hs b/compiler/nativeGen/SPARC/Regs.hs
index 8ad400f..cd19138 100644
--- a/compiler/nativeGen/SPARC/Regs.hs
+++ b/compiler/nativeGen/SPARC/Regs.hs
@@ -95,22 +95,21 @@ virtualRegSqueeze cls vr
 	 -> case vr of
 	 	VirtualRegI{}		-> _ILIT(1)
 		VirtualRegHi{}		-> _ILIT(1)
-		VirtualRegF{}		-> _ILIT(0)
-		VirtualRegD{}		-> _ILIT(0)
+                _other                  -> _ILIT(0)
 
 	RcFloat
 	 -> case vr of
-	 	VirtualRegI{}		-> _ILIT(0)
-		VirtualRegHi{}		-> _ILIT(0)
 		VirtualRegF{}		-> _ILIT(1)
 		VirtualRegD{}		-> _ILIT(2)
+                _other                  -> _ILIT(0)
 
 	RcDouble
 	 -> case vr of
-	 	VirtualRegI{}		-> _ILIT(0)
-		VirtualRegHi{}		-> _ILIT(0)
 		VirtualRegF{}		-> _ILIT(1)
 		VirtualRegD{}		-> _ILIT(1)
+                _other                  -> _ILIT(0)
+
+        _other -> _ILIT(0)
 
 {-# INLINE realRegSqueeze #-}
 realRegSqueeze :: RegClass -> RealReg -> FastInt
@@ -141,6 +140,7 @@ realRegSqueeze cls rr
 			
 		RealRegPair{}		-> _ILIT(1)
 	 		 	 	
+        _other -> _ILIT(0)
  	
 -- | All the allocatable registers in the machine, 
 --	including register pairs.
@@ -283,7 +283,7 @@ regDotColor reg
  = case classOfRealReg reg of
  	RcInteger	-> text "blue"
 	RcFloat		-> text "red"
-	RcDouble	-> text "green"
+	_other          -> text "green"