X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=blobdiff_plain;f=includes%2FMachRegs.h;h=d6075326db47eb88b3970ccb79d14f460076dfca;hp=793c6428644e2b557ee7598982920f8e19d167a7;hb=f9288086f935c97812b2d80defcff38baf7b6a6c;hpb=2d0adf8f0729cf8a4d988eaac48a480378b191ce diff --git a/includes/MachRegs.h b/includes/MachRegs.h index 793c642..d607532 100644 --- a/includes/MachRegs.h +++ b/includes/MachRegs.h @@ -95,7 +95,6 @@ s0 $9 Sp s2 $11 SpLim s3 $12 Hp - s4 $13 HpLim t8 $22 NCG_reserved t12 $27 NCG_reserved -------------------------------------------------------------------------- */ @@ -134,7 +133,6 @@ # define REG_SpLim 11 # define REG_Hp 12 -# define REG_HpLim 13 # define NCG_Reserved_I1 22 # define NCG_Reserved_I2 27 @@ -189,7 +187,6 @@ #define REG_SpLim r6 #define REG_Hp r7 -#define REG_HpLim r8 #define NCG_Reserved_I1 r28 #define NCG_Reserved_I2 r29 @@ -215,7 +212,7 @@ esi R1 edi Hp - Leaving SpLim, and HpLim out of the picture. + Leaving SpLim out of the picture. -------------------------------------------------------------------------- */ @@ -284,12 +281,12 @@ #define REG_Sp rbp #define REG_Hp r12 #define REG_R1 rbx -#define REG_R2 rsi -#define REG_R3 rdi -#define REG_R4 r8 -#define REG_R5 r9 -#define REG_SpLim r14 -#define REG_HpLim r15 +#define REG_R2 r14 +#define REG_R3 rsi +#define REG_R4 rdi +#define REG_R5 r8 +#define REG_R6 r9 +#define REG_SpLim r15 #define REG_F1 xmm1 #define REG_F2 xmm2 @@ -299,10 +296,10 @@ #define REG_D1 xmm5 #define REG_D2 xmm6 -#define CALLER_SAVES_R2 #define CALLER_SAVES_R3 #define CALLER_SAVES_R4 #define CALLER_SAVES_R5 +#define CALLER_SAVES_R6 #define CALLER_SAVES_F1 #define CALLER_SAVES_F2 @@ -312,7 +309,7 @@ #define CALLER_SAVES_D1 #define CALLER_SAVES_D2 -#define MAX_REAL_VANILLA_REG 5 +#define MAX_REAL_VANILLA_REG 6 #define MAX_REAL_FLOAT_REG 4 #define MAX_REAL_DOUBLE_REG 2 #define MAX_REAL_LONG_REG 0 @@ -361,7 +358,6 @@ #define REG_SpLim d3 #define REG_Hp d4 -#define REG_HpLim d5 #define REG_R1 a5 #define REG_R2 d6 @@ -425,7 +421,6 @@ #define REG_SpLim 21 #define REG_Hp 22 -#define REG_HpLim 23 #define REG_Base 30 @@ -500,7 +495,6 @@ #define REG_SpLim r24 #define REG_Hp r25 -#define REG_HpLim r26 #define REG_Base r27 @@ -543,13 +537,16 @@ #define REG_SpLim loc26 #define REG_Hp loc27 -#define REG_HpLim loc28 #endif /* ia64 */ /* ----------------------------------------------------------------------------- The Sun SPARC register mapping + !! IMPORTANT: if you change this register mapping you must also update + compiler/nativeGen/SPARC/Regs.hs. That file handles the + mapping for the NCG. This one only affects via-c code. + The SPARC register (window) story: Remember, within the Haskell Threaded World, we essentially ``shut down'' the register-window mechanism---the window doesn't move at all while in this World. It @@ -559,18 +556,49 @@ output registers visible in one register window. The 8 %g (global) registers are visible all the time. - %o0..%o7 not available; can be zapped by callee - (%o6 is C-stack ptr; %o7 hold ret addrs) - %i0..%i7 available (except %i6 is used as frame ptr) - (and %i7 tends to have ret-addr-ish things) - %l0..%l7 available - %g0..%g4 not available; prone to stomping by division, etc. - %g5..%g7 not available; reserved for the OS - - Note: %g3 is *definitely* clobbered in the builtin divide code (and - our save/restore machinery is NOT GOOD ENOUGH for that); discretion - being the better part of valor, we also don't take %g4. - + zero: always zero + scratch: volatile across C-fn calls. used by linker. + app: usable by application + system: reserved for system + + alloc: allocated to in the register allocator, intra-closure only + + GHC usage v8 ABI v9 ABI + Global + %g0 zero zero zero + %g1 alloc scratch scrach + %g2 alloc app app + %g3 alloc app app + %g4 alloc app scratch + %g5 system scratch + %g6 system system + %g7 system system + + Output: can be zapped by callee + %o0-o5 alloc caller saves + %o6 C stack ptr + %o7 C ret addr + + Local: maintained by register windowing mechanism + %l0 alloc + %l1 R1 + %l2 R2 + %l3 R3 + %l4 R4 + %l5 R5 + %l6 alloc + %l7 alloc + + Input + %i0 Sp + %i1 Base + %i2 SpLim + %i3 Hp + %i4 alloc + %i5 R6 + %i6 C frame ptr + %i7 C ret addr + The paired nature of the floating point registers causes complications for the native code generator. For convenience, we pretend that the first 22 fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are @@ -627,21 +655,31 @@ #define REG_F2 f23 #define REG_F3 f24 #define REG_F4 f25 + +/* for each of the double arg regs, + Dn_2 is the high half. */ + #define REG_D1 f2 +#define REG_D1_2 f3 + #define REG_D2 f4 +#define REG_D2_2 f5 #define REG_Sp i0 #define REG_SpLim i2 #define REG_Hp i3 -#define REG_HpLim i4 +#define REG_Base i1 + +/* #define NCG_SpillTmp_I1 g1 #define NCG_SpillTmp_I2 g2 #define NCG_SpillTmp_F1 f26 #define NCG_SpillTmp_F2 f27 #define NCG_SpillTmp_D1 f6 #define NCG_SpillTmp_D2 f8 +*/ #define NCG_FirstFloatReg f22