X-Git-Url: http://git.megacz.com/?p=ghc-hetmet.git;a=blobdiff_plain;f=includes%2FSMP.h;h=af4174fca601b285d1a960ae16f5cacc34f5693f;hp=68f16905c6241b78efa72092e7c7415e6e90fb70;hb=143f4381d242e4a1c3174e8a0732a1e48f00a1aa;hpb=b19bcfd953fdb10059753c1270ac1e4631da0f53

diff --git a/includes/SMP.h b/includes/SMP.h
index 68f1690..af4174f 100644
--- a/includes/SMP.h
+++ b/includes/SMP.h
@@ -48,6 +48,16 @@ xchg(StgPtr p, StgWord w)
         :"=r" (result)
         :"r" (w), "r" (p)
     );
+#elif sparc_HOST_ARCH
+    result = w;
+    __asm__ __volatile__ (
+        "swap %1,%0"
+	: "+r" (result), "+m" (*p)
+	: /* no input-only operands */
+      );
+#elif !defined(WITHSMP)
+    result = *p;
+    *p = w;
 #else
 #error xchg() unimplemented on this architecture
 #endif
@@ -76,10 +86,26 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
         "       stwcx.    %2, 0, %3\n"
         "       bne-      1b\n"
         "2:"
-        :"=r" (result)
+        :"=&r" (result)
         :"r" (o), "r" (n), "r" (p)
+        :"cc", "memory"
     );
     return result;
+#elif sparc_HOST_ARCH
+    __asm__ __volatile__ (
+	"cas [%1], %2, %0"
+	: "+r" (n)
+	: "r" (p), "r" (o)
+	: "memory"
+    );
+    return n;
+#elif !defined(WITHSMP)
+    StgWord result;
+    result = *p;
+    if (result == o) {
+        *p = n;
+    }
+    return result;
 #else
 #error cas() unimplemented on this architecture
 #endif
@@ -101,6 +127,11 @@ write_barrier(void) {
     __asm__ __volatile__ ("" : : : "memory");
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
+#elif sparc_HOST_ARCH
+    /* Sparc in TSO mode does not require write/write barriers. */
+    __asm__ __volatile__ ("" : : : "memory");
+#elif !defined(WITHSMP)
+    return;
 #else
 #error memory barriers unimplemented on this architecture
 #endif
@@ -116,7 +147,6 @@ write_barrier(void) {
 INLINE_HEADER StgInfoTable *
 lockClosure(StgClosure *p)
 {
-#if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
     StgWord info;
     do {
 	nat i = 0;
@@ -126,21 +156,14 @@ lockClosure(StgClosure *p)
 	} while (++i < SPIN_COUNT);
 	yieldThread();
     } while (1);
-#else
-   ACQUIRE_SM_LOCK
-#endif
 }
 
 INLINE_HEADER void
 unlockClosure(StgClosure *p, StgInfoTable *info)
 {
-#if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
     // This is a strictly ordered write, so we need a wb():
     write_barrier();
     p->header.info = info;
-#else
-    RELEASE_SM_LOCK;
-#endif
 }
 
 #else /* !THREADED_RTS */